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GM5020-H の電気的特性と機能

GM5020-HのメーカーはGenesisです、この部品の機能は「Graphics Processing IC providing high-quality images」です。


製品の詳細 ( Datasheet PDF )

部品番号 GM5020-H
部品説明 Graphics Processing IC providing high-quality images
メーカ Genesis
ロゴ Genesis ロゴ 




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GM5020-H Datasheet, GM5020-H PDF,ピン配置, 機能
www.DataSheet4U.com
Genesis Microchip Publication
DATA SHEET
gm5020/gm5020-H
Sections in this document and all other related documentation that mention HDCP refer
only to the gm5020-H (HDCP-enabled) chip. All other sections apply to both the gm5020-H
chip and the gm5020 (non-HDCP) chip.
Publication number: C5020-DAT-01Q
Publication date: February 2002
Genesis Microchip Inc.
165 Commerce Valley Dr. West Thornhill ON Canada L3T 7V8 Tel: (905) 889-5400 Fax: (905) 889-5422
2150 Gold Street PO Box 2150 Alviso CA USA 95002 Tel: (408) 262-6599 Fax: (408) 262-6365
4F, No. 24, Ln 123, Sec 6, Min-Chung E. Rd. Taipei Taiwan Tel: (2) 2791-0118 Fax: (2) 2791-0196
143-37 Hyundai Tower Unit 902 Samsung-dong Kangnam-gu Seoul Korea 135-090 Tel: (82-2) 553-5693 Fax: (82-2) 552-4942
www.genesis-microchip.com / [email protected]

1 Page





GM5020-H pdf, ピン配列
Genesis Microchip
gm5020 / gm5020-H Data Sheet
Document
C5020-DAT-01A
C5020-DAT-01B
C5020-DAT-01C
C5020-DAT-01D
C5020-DAT-01E
C5020-DAT-01F
C5020-DAT-01G
C5020-DAT-01H
C5020-DAT-01I
C5020-DAT-01J
C5020-DAT-01K
C5020-DAT-01L
Document history
Description
Initial Release
PWM feature documented
Pin R1 (HDATA1) does not require pull-up (See Table 5).
FSADDR7 bootstrap functionality corrected.
Figure 59 clarified.
Character attribute word mapping corrections in Sections 0 and 0.
Figure 1 – second EDID EPROM added to clarify the example.
YUV(7:0) incorporate General Purpose Inputs (GPIs). See Section
4.19.1 and Table 4.
Section 4.19.1,General Purpose Inputs and Outputs (GPIO’s) added.
RealColor ™ Flesh tone Adjustment feature documented.
Revised Preliminary AC Characteristics (5.2)
Revised Section 5.1 Preliminary DC Characteristics (Power Figures)
Revised Table 3 (TCLK, XTAL)
Revised Section 4.1 Clocking Options
Added Sections 4.10.10 Input Dithering / Compression and
4.15.2 Output Dithering
Minor clarifications to Sections: 4.2.1; 4.3.4; 4.10.3; 4.19.2 and 4.19.3
and to Figures 1 and 3
Revised Table 3 (TCLK, XTAL)
Revised Section 4.1 Clocking Options: add 2.7 K pulldown resistor,
TCLK to ground, to maintain correct duty cycle for oscillator
Host Interface Port, HDATA(3:0) pins changed to indicate upper nibble
transferred first followed by lower nibble.
Minor clarification to REXT pin description
Changed VDD_3.3 and VDD_2.5 MIN and MAX values from TYP +/-
10% to TYP +/- 5% in Table 17.
PWM0 and PWM1 have same functionality 4.19.2.
Cosmetic changes to Table 18 - Maximum Speed of Operation
Modified recommended HSYNC input circuit in Figure 6 - Example
Signal Terminations
Modified Figure 4 –Clock Generation Options for gm5020
Added note “(400mV typical hysteresis)” to all Schmitt trigger inputs in
Section 3 - Pin List.
Amended I/O column in Table 6 – Display Port Signals
In section 1.2 - Features and Analog RGB Input Port - changed SXGA to
UXGA. In Analog RGB Input Port, changed frequency to 60Hz. In Ultra-
Reliable DVI Receiver, changed frequency to 165MHz.
In section 4.3.4, changed range to “10MHz to 162MHz.”
In Table 12 changed input clock to 165MHz.
In Table 16, changed θJC rating to 7.8.
In Table 17, made extensive changes to parameters and ratings.
In Table 18, included maximum speed of operation (200MHz) for R_CLK
Reference Clock. Changed TMDS clock to 165MHz. Changed ADC
Clock to 162MHz. Changed F_CLK_Frame Store Clock speed to
144MHz.
In section 14.16.1.1, changed number of words from 3324 to 3594.
In section 6, changed Speed to 162MHz.
In section 3, corrected references to certain signals.
In first sentence of section 4.16.1.4, corrected reference to bit setting.
In Table 16, changed Input Voltage (5V tolerant inputs) Max to 5.5V
In Table 17, included more details about supply current specifications.
Date
June 2000
June 2000
July 2000
August 2000
August 2000
October 2000
October 2000
Jan. 2001
Feb. 2001
April 2001
July 2001
July 2001
February 2002
iii C5020-DAT-01Q


3Pages


GM5020-H 電子部品, 半導体
Genesis Microchip
gm5020/gm5020-H Data Sheet
4.10.4 SDRAM Power On Sequence .............................................................................. 41
4.10.5 SDRAM Power Down ........................................................................................... 41
4.10.6 Pan and Crop Operations..................................................................................... 42
4.10.7 Double Buffering Frame Store Bandwidth Requirements ..................................... 42
4.10.8 Freeze Frame....................................................................................................... 42
4.10.9 Interlaced Formats and De-interlacing ................................................................. 42
4.11 Scaling............................................................................................................................ 43
4.11.1 Pixel Replication Scaling ...................................................................................... 43
4.11.2 Vertical Shrink ...................................................................................................... 43
4.11.3 Adaptive Contrast Enhancement (ACE) ............................................................... 43
4.12 Gamma Correction LUT.................................................................................................. 44
4.12.1 Gamma Correction ............................................................................................... 44
4.12.2 Moiré Cancellation................................................................................................ 45
4.13 Display Timing and Control............................................................................................. 46
4.13.1 Display Clock Generation – Display Digital Direct Synthesis Block (DDDS) ........ 46
4.13.2 Display Synchronization ....................................................................................... 47
4.13.3 Display Port Timing .............................................................................................. 49
4.14 Data Path Bypass Options.............................................................................................. 51
4.15 OSD................................................................................................................................ 53
4.15.1 Character Mapped OSD ....................................................................................... 53
4.15.2 Bitmapped OSD ................................................................................................... 59
4.15.3 Color Look-up Table (LUT)................................................................................... 59
4.15.4 Multiple OSD Windows......................................................................................... 59
4.15.5 OSD Stretch ......................................................................................................... 59
4.15.6 Blending ............................................................................................................... 59
4.15.7 OSD Merge .......................................................................................................... 60
4.16 On-Chip Microprocessor................................................................................................. 61
4.17 Bootstrap Configuration .................................................................................................. 62
4.18 Host Interface ................................................................................................................. 63
4.18.1 2-wire Configuration ............................................................................................. 63
4.18.2 6-Wire Configuration ............................................................................................ 66
4.19 Miscellaneous Functions ................................................................................................ 69
4.19.1 General Purpose Inputs and Outputs (GPIO’s) .................................................... 69
4.19.2 Pulse Width Modulation (PWM) Back Light Control ............................................. 69
4.19.3 Low Power State .................................................................................................. 69
5. Electrical Specifications .......................................................................................................... 70
5.1 DC Characteristics............................................................................................................ 70
5.2 Preliminary AC Characteristics ......................................................................................... 72
6. Ordering Information ............................................................................................................... 76
7. Mechanical Specifications....................................................................................................... 77
February 2002
vi
C5020-DAT-01Q

6 Page



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部品番号部品説明メーカ
GM5020-H

Graphics Processing IC providing high-quality images

Genesis
Genesis


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