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U63716 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 U63716
部品説明 CapStore 2K x 8 nvSRAM
メーカ Simtek
ロゴ Simtek ロゴ 



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U63716 Datasheet, U63716 PDF,ピン配置, 機能
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Obsolete - Not Recommended for New Designs
U63716
CapStore 2K x 8 nvSRAM
Features
Description
CMOS non- volatile static RAM The U63716 has two separate
2048 x 8 bits
modes of operation: SRAM mode
70 ns Access Time
and nonvolatile mode. In SRAM
35 ns Output Enable Access Time mode, the memory operates as an
ICC = 15 mA at 200 ns Cycle Time
Unlimited Read and Write Cycles
ordinary static RAM. In non-volatile
operation, data is transferred in
to SRAM
Automatic STORE to EEPROM
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
on Power Down using charge
mode SRAM functions are disab-
stored in an integrated capacitor
Software initiated STORE
Automatic STORE Timing
106 STORE cycles to EEPROM
100 years data retention in
led.
The U63716 is a static RAM with a
non-volatile electrically erasable
PROM (EEPROM) element incor-
porated in each static memory cell.
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
Unlimited RECALL cycles from
The SRAM can be read and written
an unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
EEPROM
Single 5 V ± 10 % Operation
Operating temperature range:
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
0 to 70 °C
using charge stored in an integra-
-40 to 85 °C
QS 9000 Quality Standard
ESD protection > 2000 V
ted capacitor. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
(MIL STD 883C M3015.7)
RoHS compliance and Pb- free
Package: PDIP24 (600 mil)
automatically on power up. The
U63716 combines the ease of use
of an SRAM with nonvolatile data
integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U63716 is pin compatible with
standard SRAMs and standard bat-
tery backed SRAMs.
Pin Configuration
Pin Description
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6 PDIP
7 24
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
March 31, 2006
STK Control #ML0053
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
1 Rev 1.0

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