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PDF U635H16 Data sheet ( Hoja de datos )
| Número de pieza | U635H16 | |
| Descripción | PowerStore 2K x 8 nvSRAM | |
| Fabricantes | Simtek | |
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Obsolete - Not Recommended for New Designs
U635H16
PowerStore 2K x 8 nvSRAM
Features
• High-performance CMOS non-
volatile static RAM 2048 x 8 bits
• 25, 35 and 45 ns Access Times
• 12, 20 and 25 ns Output Enable
Access Times
• ICC = 15 mA at 200 ns Cycle Time
• Automatic STORE to EEPROM
on Power Down using system
capacitance
• Software initiated STORE
(STORE Cycle Time < 10 ms)
• Automatic STORE Timing
• 106 STORE cycles to EEPROM
• 100 years data retention in
EEPROM
• Automatic RECALL on Power Up
• Software RECALL Initiation
(RECALL Cycle Time < 20 μs)
• Unlimited RECALL cycles from
EEPROM
• Single 5 V ± 10 % Operation
• Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
• QS 9000 Quality Standard
• ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
• RoHS compliance and Pb- free
• Packages: PDIP24 (600 mil)
SOP24 (300 mil)
Description
The U635H16 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U635H16 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in system
capacitance.
Transfers from the EEPROM to the
SRAM (the RECALL operation)
take place automatically on power
up. The U635H16 combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
Pin Description
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1 24
2 23
3 22
4 21
5 20
6 PDIP 19
7
SOP
24
18
8 17
9 16
10 15
11 14
12 13
VCC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
March 31, 2006
STK Control #ML0050
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
1 Rev 1.0
1 page  
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
Ai
DQi
Output
tcR (1)
Address Valid
ta(A) (2)
Previous Data Valid
tv(A) (9)
Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
Ai
E
G
DQi
Output
ICC
tcR (1)
Address Valid
ta(A) (2)
ta(E) (3)
ten(E) (7)
ta(G) (4)
High Impedance
ten(G) (8)
ACTIVE
tPU (10)
STANDBY
tPD (11)
tdis(E) (5)
tdis(G) (6)
Output Data Valid
U635H16
No.
Switching Characteristics
Write Cycle
Symbol
Alt. #1 Alt. #2 IEC
25 35 45
Unit
Min. Max. Min. Max. Min. Max.
12 Write Cycle Time
tAVAV
tAVAV
tcW
25
35
45
13 Write Pulse Width
tWLWH
tw(W) 20 30 35
14 Write Pulse Width Setup Time
tWLEH tsu(W) 20 30 35
15 Address Setup Time
tAVWL
tAVEL
tsu(A)
0
0
0
16 Address Valid to End of Write
tAVWH tAVEH tsu(A-WH) 20
30
35
17 Chip Enable Setup Time
tELWH
tsu(E) 20 30 35
18 Chip Enable to End of Write
tELEH
tw(E)
20
30
35
19 Data Setup Time to End of Write
tDVWH tDVEH tsu(D) 12
18
20
20 Data Hold Time after End of Write tWHDX tEHDX th(D)
0
0
0
21 Address Hold after End of Write
tWHAX tEHAX
th(A)
0
0
0
22 W LOW to Output in High-Zh, i
tWLQZ
tdis(W) 10 13 15
23 W HIGH to Output in Low-Z
tWHQX
ten(W)
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
March 31, 2006
STK Control #ML0050
5
Rev 1.0
5 Page 
U635H16
Device Operation
The U635H16 has two separate modes of operation:
SRAM mode and nonvolatile mode. In SRAM mode,
the memory operates as a standard fast static RAM. In
nonvolatile mode, data is transferred from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence and are also automatically initiated
when the power supply voltage level of the chip falls
below VSWITCH. RECALL operations are automatically
initiated upon power up and may also occur when the
VCC rises above VSWITCH, after a low power condition.
RECALL cycles may also be initiated by a software
sequence.
SRAM READ
The U635H16 performs a READ cycle whenever E and
G are LOW and W are HIGH. The address specified on
pins A0 - A10 determines which of the 2048 data bytes
will be accessed. When the READ is initiated by an
address transition, the outputs will be valid after a delay
of tcR. If the READ is initiated by E or G, the outputs will
be valid at ta(E) or at ta(G), whichever is later. The data
outputs will repeatedly respond to address changes
within the tcR access time without the need for transition
on any control input pins, and will remain valid until
another address change or until E or G is brought
HIGH or W is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid tsu(D) before the end of a W controlled WRITE or
tsu(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the en-
tire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
Automatic STORE
The U635H16 uses the intrinsic system capacitance to
perform an automatic STORE on power down. As long
as the system power supply take at least tPDSTORE to
decay from VSWITCH down to 3.6 V the U635H16 will
safely and automatically STORE the SRAM data in
EEPROM on power down.
In order to prevent unneeded STORE operations, auto-
matic STORE will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether or
not a WRITE operation has taken place.
Automatic RECALL
During power up an automatic RECALL takes place.
After any low power condition (VCC < VSWITCH) an inter-
nal RECALL request may be latched. When VCC once
again exceeds the sense voltage of VSWITCH, a reque-
sted RECALL cycle will automatically be initiated and
will take tRESTORE to complete.
If the U635H16 is in a WRITE state at the end of a
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 KΩ resistor should be
connected between W and system VCC.
Software Nonvolatile STORE
The U635H16 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U635H16 implements nonvolatile operation
while remaining compatible with standard 2K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is performed first, followed by a
parallel programming of all nonvolatile elements. Once
a STORE cycle is initiated, further inputs and outputs
are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
To initiate the STORE cycle the following READ
sequence must be performed:
1. Read address 000 (hex) Valid READ
2. Read address 555 (hex) Valid READ
3. Read address 2AA (hex) Valid READ
4. Read address 7FF (hex) Valid READ
5. Read address 0F0 (hex) Valid READ
6. Read address 70F (hex) Initiate STORE
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles are used in the sequence, although it
is not necessary that G is LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
March 31, 2006
STK Control #ML0050
11
Rev 1.0
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet U635H16.PDF ] | |
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