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PDF U630H16P Data sheet ( Hoja de datos )
| Número de pieza | U630H16P | |
| Descripción | HardStore 2K x 8 nvSRAM | |
| Fabricantes | Simtek Corporation | |
| Logotipo |  |
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Obsolete - Not Recommended for New Designs
U630H16P
HardStore 2K x 8 nvSRAM
Features
Description
• High-performance CMOS nonvo-
latile static RAM 2048 x 8 bits
• 35 ns Access Times
• 20 ns Output Enable Access
Times
• Hardware and Software STORE
Initiation
(STORE Cycle Time < 10 ms)
• Automatic STORE Timing
• 106 STORE cycles to EEPROM
• 100 years data retention in
EEPROM
• Automatic RECALL on Power Up
• Hardware and Software RECALL
Initiation
(RECALL Cycle Time < 20 μs)
• Unlimited RECALL cycles from
EEPROM
• Unlimited Read and Write to
SRAM
• Single 5 V ± 10 % Operation
• Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
• QS 9000 Quality Standard
• ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
• Package: PLCC32
The U630H16P has two separate
modes of operation: SRAM mode
and nonvolatile mode, determined
by the state of the NE pin.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
nonvolatile operation, data is trans-
ferred in parallel from SRAM to
EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
The U630H16P is a fast static RAM
(35 ns), with a nonvolatile electri-
cally erasable PROM (EEPROM)
element incorporated in each static
memory cell. The SRAM can be
read and written an unlimited num-
ber of times, while independent
nonvolatile data resides in
EEPROM. Data transfers from the
SRAM to the EEPROM (the
STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through the state of the NE pin or
through software sequences.
The U630H16P combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
A6
A5
A4
A3
A2
A1
A0
n.c.
DQ0
4 3 2 1 32 31 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
A8
A9
n.c.
n.c.
G
A10
E
DQ7
DQ6
Top View
March 31, 2006
STK Control #ML0037
Pin Description
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
NE
VCC
VSS
n.c.
(VCC)
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Nonvolatile Enable
Power Supply Voltage
Ground
not connected
Power Supply Voltage
(optional)
1 Rev 1.0
1 page  
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = NE = VIH)f
Ai
DQi
Output
tcR (1)
Address Valid
ta(A) (2)
Previous Data Valid
tv(A) (9)
Output Data Valid
U630H16P
Read Cycle 2: G-, E-controlled (during Read cycle: W = NE = VIH)g
Ai
E
G
DQi
Output
ICC
tcR (1)
Address Valid
ta(A) (2)
ta(E) (3)
ten(E) (7)
ta(G) (4)
ten(G) (8)
High Impedance
ACTIVE
tPU (10)
STANDBY
tdis(E)
(5)
tdis(G) (6)
Output Data Valid
tPD (11)
No. Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
Symbol
Alt. #1 Alt. #2 IEC
tAVAV
tWLWH
tAVWL
tAVWH
tELWH
tDVWH
tWHDX
tWHAX
tWLQZ
tWHQX
tAVAV
tcW
tw(W)
tWLEH tsu(W)
tAVEL tsu(A)
tAVEH tsu(A-WH)
tsu(E)
tELEH tw(E)
tDVEH tsu(D)
tEHDX th(D)
tEHAX th(A)
tdis(W)
ten(W)
March 31, 2006
STK Control #ML0037
5
35
Min.
Max.
35
30
30
0
30
30
30
18
0
0
13
5
Rev 1.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5 Page 
U630H16P
Software Mode Selection
E
W
A10 - A0
(hex)
LH
LH
000
555
2AA
7FF
0F0
70F
000
555
2AA
7FF
0F0
70E
Mode
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
I/O
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Power
Active
ICC2
Active
Notes
s, t
s, t
s, t
s, t
s, t
s
s, t
s, t
s, t
s, t
s, t
s
s: The six consecutive addresses must be in order listed (000, 555, 2AA, 7FF, 0F0, 70F) for a Store cycle or (000, 555, 2AA,
7FF, 0F0, 70E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and
diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 000, 555, 2AA, 7FF, 0F0, 39C.
t: I/O state assumes that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G.
Symbol
No. Software Controlled STORE/RECALL
Cycles, u
Alt.
IEC
25 35 45
Unit
Min. Max. Min. Max. Min. Max.
25 STORE/RECALL Initiation Time
26 Chip Enable to Output Inactivev
27 STORE Cycle Timew
28 RECALL Cycle Timel
29 Address Setup to Chip Enablex
30 Chip Enable Pulse Widthx, y
31 Chip Disable to Address Changex
tAVAV tcR 25 35 45 ns
tELQZ tdis(E)SR
600
600
600 ns
tELQXS td(E)S 10 10 10 ms
tELQXR td(E)R 20 20 20 μs
tAVELN tsu(A)SR 0 0 0 ns
tELEHN tw(E)SR 20 25 35 ns
tEHAXN th(A)SR
0
0
0 ns
u: The software sequence is clocked with E controlled READs.
v: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
w: Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
x: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
y: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
March 31, 2006
STK Control #ML0037
11
Rev 1.0
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet U630H16P.PDF ] | |
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