PDF STK15C68 Data sheet ( Hoja de datos )

Número de pieza	STK15C68
Descripción	CMOS Nonvolatile Static RAM
Fabricantes	Simtek
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No Preview Available ! www.DataSheet4U.com STK15C68 8K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM Obsolete - Not Recommend for new Deisgns FEATURES • Nonvolatile Storage without Battery Problems • Directly Replaces 8K x 8 Static RAM, Battery- Backed RAM or EEPROM • 25ns, 35ns and 45ns Access Times • STORE to Nonvolatile Elements Initiated by Software or AutoStore™ on Power Down • RECALL to SRAM Initiated by Software or Power Restore • 10mA Typical ICC at 200ns Cycle Time • Unlimited READ, WRITE and RECALL Cycles • 1,000,000 STORE Cycles to Nonvolatile Ele- ments • 100-Year Data Retention over Full Industrial Temperature Range • No Data Loss from Undershoot • Commercial and Industrial Temperatures • 28-Pin 600 or 300 mil PDIP and 350 mil SOIC Packages DESCRIPTION The STK15C68 is a fast SRAM with a nonvolatile ele- ment incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in Nonvolatile Elements. Data transfers from the SRAM to the Nonvolatile Elements (the STORE operation) can take place automatically on power down using charge stored in system capacitance. Transfers from the Non- volatile Elements to the SRAM (the RECALL operation) take place automatically on restoration of power. Initia- tion of STORE and RECALL cycles can also be con- trolled by entering control sequences on the SRAM inputs. The STK15C68 is pin-compatible with 8k x 8 SRAMs and battery-backed SRAMs, allowing direct substitution while enhancing performance. A similar device (STK16C68) with an internally integrated capacitor is available for systems with very fast slew rates. The STK12C68, which uses an external capaci- tor, is an alternative for these applications. BLOCK DIAGRAM A5 A6 A7 A8 A9 A11 A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 QUANTUM TRAP 128 x 512 STATIC RAM ARRAY 128 x 512 STORE RECALL COLUMN I/O COLUMN DEC A0 A1 A2 A3 A4 A10 STORE/ RECALL CONTROL VCC POWER CONTROL SOFTWARE DETECT A0 - A12 G E W PIN CONFIGURATIONS NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 VCC 27 W 26 NC 25 A8 24 A9 23 A11 22 G 21 A10 20 E 19 DQ7 18 DQ6 17 DQ5 16 DQ4 15 DQ3 28 - 300 PDIP 28 - 600 PDIP 28 - 350 SOIC PIN NAMES A0 - A12 W DQ0 - DQ7 E G VCC VSS Address Inputs Write Enable Data In/Out Chip Enable Output Enable Power (+ 5V) Ground March 2006 1 Document Control # ML0009 rev 0.2 1 page AutoStore™/POWER-UP RECALL SYMBOLS NO. Standard PARAMETER 22 tRESTORE 23 tSTORE 24 tDELAY 25 VSWITCH 26 VRESET Power-up RECALL Duration STORE Cycle Duration Time Allowed to Complete SRAM Cycle Low Voltage Trigger Level Low Voltage Reset Level Note k: tRESTORE starts from the time VCC rises above VSWITCH. AutoStore™/POWER-UP RECALL VCC 25 5V VSWITCH 26 VRESET AutoStore™ POWER-UP RECALL W 22 tRESTORE DQ (DATA OUT) 24 tDELAY STK15C68 (VCC = 5.0V ± 10%) STK15C68 MIN MAX UNITS NOTES 550 μs 10 ms k g 1 μs 4.0 4.5 V g 3.6 V e 23 tSTORE POWER-UP BROWN OUT RECALL NO STORE DUE TO NO SRAM WRITES NO RECALL (VCC DID NOT GO BELOW VRESET) BROWN OUT AutoStore™ NO RECALL (VCC DID NOT GO BELOW VRESET) BROWN OUT AutoStore™ RECALL WHEN VCC RETURNS ABOVE VSWITCH March 2006 5 Document Control # ML0009 rev 0.2 5 Page

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