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PDF STK14C88-3 Data sheet ( Hoja de datos )
| Número de pieza | STK14C88-3 | |
| Descripción | 32Kx8 AutoStore nvSRAM | |
| Fabricantes | Simtek | |
| Logotipo |  |
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FEATURES
• 35, 45 ns Read Access & R/W Cycle Time
• Unlimited Read/Write Endurance
• Automatic Non-volatile STORE on Power Loss
• Non-Volatile STORE Under Hardware or
Software Control
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
• 1 Million STORE Cycles
• 100-Year Non-volatile Data Retention
• Single 3.3V ± 10% Power Supply
• Commercial and Industrial Temperatures
• 32-Pin 300 mil SOIC and 600 mil PDIP Pack-
ages (RoHS-Compliant)
STK14C88-3
32Kx8 AutoStore nvSRAM
DESCRIPTION
The Simtek STK14C88-3 is a 256Kb fast static RAM
with a non-volatile Quantum Trap storage element
included with each memory cell.
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM.
Data transfers automatically to the non-volatile stor-
age cells when power loss is detected (the STORE
operation). On power up, data is automatically
restored to the SRAM (the RECALL operation). Both
STORE and RECALL operations are also available
under software control.
The Simtek nvSRAM is the first monolithic non-vola-
tile memory to offer unlimited writes and reads. It is
the highest performance, most reliable non-volatile
memory available.
BLOCK DIAGRAM
A5
A6
A7
A8
A9
A 11
A 12
A 13
A 14
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
Quatum Trap
512 X 512
STATIC RAM
ARRAY
512 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A10
VCCX
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
A13 – A 0
G
E
W
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
1 Document Control #ML0015 Rev 0.6
February 2007
1 page  
SRAM READ CYCLES #1 & #2
STK14C88-3
(VCC = 3V - 3.6V)e
SYMBOLS
NO.
#1, #2
Alt.
PARAMETER
STK14C88-3-35 STK14C88-3-45
UNITS
MIN MAX MIN MAX
1 tELQV
2 tAVAVg
3 tAVQVh
4 tGLQV
5 tAXQXh
6 tELQX
7 tEHQZi
8 tGLQX
9 tGHQZi
10 tELICCHf
11 tEHICCLf
tACS
tRC
tAA
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
35 45 ns
35 45 ns
35 45 ns
15 20 ns
5 5 ns
5 5 ns
13 15 ns
0 0 ns
13 15 ns
0 0 ns
35 45 ns
Note g: W and HSB must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: /O state assumes E and G < VIL and W > VIH; device is continuously selected.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
ADDRESS
DQ (DATA OUT)
5
tAXQX
2
tAVAV
3
tAVQV
DATA VALID
SRAM READ CYCLE #2: E Controlledg
ADDRESS
E
6
tELQX
2
tAVAV
1
tELQV
G
DQ (DATA OUT)
ICC
8
tGLQX
4
tGLQV
10
tELICCH
STANDBY
ACTIVE
11
tEHICCL
7
tEHQZ
9
tGHQZ
DATA VALID
Document Control #ML0015 Rev 0.6
February 2007
5
5 Page 
STK14C88-3
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of E controlled READ opera-
tions must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
information is transferred into the SRAM cells. After
the tRECALL cycle time the SRAM will once again be
ready for READ and WRITE operations. The RECALL
operation in no way alters the data in the nonvolatile
elements. The nonvolatile data can be recalled an
unlimited number of times.
AutoStore OPERATION
The STK14C88-3 can be powered in one of three
modes.
During normal AutoStore operation, the STK14C88-
3 will draw current from VCCX to charge a capacitor
connected to the VCAP pin. This stored charge will be
used by the chip to perform a single STORE opera-
tion. After power up, when the voltage on the VCAP
pin drops below VSWITCH, the part will automatically
disconnect the VCAP pin from VCCX and initiate a
STORE operation.
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68μF and
220μF (± 20%) rated at 4.7V should be provided.
In order to prevent unneeded STORE operations,
automatic STOREs as well as those initiated by
externally driving HSB low will be ignored unless at
least one WRITE operation has taken place since the
most recent STORE or RECALL cycle. Software-
initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place.
If the power supply drops faster than 20 μs/volt
before VCCX reaches VSWITCH, then a 1 ohm resistor
should be inserted between VCCX and the system
supply to avoid momentary excess of current
between Vccx and Vcap.
10kO*
1
32
31
30
+
16 17
Figure 2: AutoStore Mode
*If HSB is not used, it should be left unconnected.
HSB OPERATION
The STK14C88-3 provides the HSB pin for control-
ling and acknowledging the STORE operations. The
HSB pin can be used to request a hardware STORE
cycle. When the HSB pin is driven low, the
STK14C88-3 will conditionally initiate a STORE oper-
ation after tDELAY; an actual STORE cycle will only
begin if a WRITE to the SRAM took place since the
last STORE or RECALL cycle. The HSB pin also acts
as an open drain driver that is internally driven low
to indicate a busy condition while the STORE (initi-
ated by any means) is in progress. Pull up this pin
with an external 10K ohm resistor to VCAP if HSB is
used as a driver.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK14C88-3
will continue SRAM operations for tDELAY. During tDELAY,
multiple SRAM READ operations may take place. If a
WRITE is in progress when HSB is pulled low it will
be allowed a time, tDELAY, to complete. However, any
SRAM WRITE cycles requested after HSB goes low
will be inhibited until HSB returns high.
The HSB pin can be used to synchronize multiple
STK14C88-3s while using a single larger capacitor.
To operate in this mode the HSB pin should be con-
nected together to the HSB pins from the other
STK14C88-3s. An external pull-up resistor to +3.3V
is required since HSB acts as an open drain pull-
down. The VCAP pins from the other STK14C88-3
Document Control #ML0015 Rev 0.6
February 2007
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet STK14C88-3.PDF ] | |
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