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PDF UPD720113 Data sheet ( Hoja de datos )
| Número de pieza | UPD720113 | |
| Descripción | USB 2.0 HUB CONTROLLER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD720113
USB 2.0 HUB CONTROLLER
The µPD720113 is a USB 2.0 hub device that complies with the Universal Serial Bus (USB) Specification Revision
2.0 and works up to 480 Mbps. USB 2.0 compliant transceivers are integrated for upstream and all downstream ports.
The µPD720113 works backward compatible either when any one of the downstream ports is connected to a USB 1.1
compliant device, or when the upstream port is connected to a USB 1.1 compliant host.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µPD720113 User’s Manual: S16619E
FEATURES
• Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
• Certified by USB implementers forum and granted the USB 2.0 high-speed Logo
• High-speed or full-speed packet protocol sequencer for Endpoint 0/1
• 7 (Max.) downstream facing ports
• All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5
Mbps) transaction.
• Supports split transaction to handle full-speed and low-speed transaction on downstream facing ports when
Hub controller is working in high-speed mode.
• One Transaction Translator per Hub and supports four non-periodic buffers
• Support self-powered mode
• Supports Over-current detection and Individual or ganged power control
• Supports configurable vendor ID, product ID, string descriptors and others with external Serial ROM
• Supports “non-removable” attribution on individual port
• Uses 30 MHz X’tal, or clock input
• 2.5 V and 3.3 V power supplies
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16618EJ3V0DS00 (3rd edition)
Date Published March 2005 NS CP (N)
Printed in Japan
The mark shows major revised points.
2003
1 page  
µPD720113
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
VDD33
VDD25
VSS
DM6
DP6
VDD33
VSS
DM7
DP7
VSS
VDD25
VSS
TEST
SCAN_MODE
VSS
LPWRM
EXROM_EN
SCL
SDA/GANG_B
VSS
Pin No.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin Name
VDD33
CSB7
PPB7
CSB6
PPB6
CSB5
PPB5
CSB4
VSS
VDD25
PPB4
CSB3
PPB3
CSB2
PPB2
CSB1
PPB1
SYSRSTB
VBUSM
VDD33
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Pin Name
VSS
X1_CLK
X2
VDD25
AVSS
RREF
AVSS(R)
AVDD
AVSS
AVDD
VSS
VDD25
VDD33
VSS
DMU
DPU
VDD25
VSS
RPU
VDD33
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin Name
DM1
DP1
VDD25
VSS
DM2
DP2
VDD33
VSS
DM3
DP3
VDD33
VSS
VDD25
VSS
DM4
DP4
VDD25
VSS
DM5
DP5
Remark AVSS(R) should be used to connect RREF through 1 % precision reference resistor of 2.43 kΩ.
Data Sheet S16618EJ3V0DS
5
5 Page 
µPD720113
DC Characteristics
Parameter
Off-state output leakage current
Output short circuit current
Low-level output current
3.3 V low-level output current
3.3 V low-level output current
5.0 V low-level output current
High-level output current
3.3 V high-level output current
3.3 V high-level output current
5.0 V high-level output current
Input leakage current
3.3 V buffer
5.0 V buffer
Symbol
IOZ
IOS Note
IOL
IOH
II
Condition
VO = VDD33, VDD25 or VSS
VOL = 0.4 V
VOL = 0.4 V
VOL = 0.4 V
VOH = 2.4 V
VOH = 2.4 V
VOH = 2.4 V
VI = VDD or VSS
VI = VDD or VSS
MIN.
MAX.
±10
−250
Unit
µA
mA
3 mA
6 mA
12 mA
−3 mA
−6 mA
−2 mA
±10 µA
±10 µA
Note The output short circuit time is measured at one second or less and is tested with only one pin on the LSI.
Data Sheet S16618EJ3V0DS
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD720113.PDF ] | |
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