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PDF A49LF040A Data sheet ( Hoja de datos )
| Número de pieza | A49LF040A | |
| Descripción | 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory | |
| Fabricantes | AMIC Technology | |
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Preliminary
A49LF040A
4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
Document Title
4 Mbit CMOS 3.3 Volt-only Low Pin Count Flash Memory
Revision History
Rev. No.
0.0
0.1
History
Initial issue
Correct the part number from A49LF040A to A49LF040AT on
page 29
Issue Date
March 3, 2006
March 28, 2006
Remark
Preliminary
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
1 page  
A49LF040A
Table 1: Pin Description
Symbol
Pin Name
A10-A0
Address
I/O7-I/O0
Data
Type
IN
I/O
Interface
A/A
Mux
LPC
Descriptions
X
Inputs for addresses during Read and Write operations in A/A Mux
mode. Row and column addresses are latched by R/C pin.
To output data during Read cycle and receive input data during
X Write cycle in A/A Mux mode. The outputs are in tri-state when
OE is high.
OE
Output Enable
IN X
To control the data output buffers.
WE Write Enable
IN X
To control the Write operations.
MODE
Interface Mode
Select
To determine which interface is operational. When held high, A/A
Mux mode is enabled and when held low, LPC mode is enabled.
IN X X This pin must be setup at power-up or before return from reset and
not change during device operation. This pin is internally pulled
down with a resistor between 20-100 K
INIT Initialize
This is the second reset pin for in-system use. INIT and RST
IN X pins are internally combined and initialize a device reset when
driven low.
ID[3:0]
Identification Inputs IN
These four pins are part of the mechanism that allows multiple
LPC devices to be attached to the same bus. To identify the
component, the correct strapping of these pins must be set. The
X boot device must have ID[3:0]=0000 and it is recommended that
all subsequent devices should use sequential up-count strapping.
These pins are internally pulled down with a resistor between 20-
100 KΩ.
GPI[4:0]
General Purpose
Inputs
IN
These individual inputs can be used for additional board flexibility.
The state of these pins can be read immediately at boot, through
X
LPC internal registers. These inputs should be at their desired
state before the start of the PCI clock cycle during which the read
is attempted, and should remain in place until the end of the Read
cycle. Unused GPI pins must not be floated.
TBL
Top Block Lock
IN
To prevent any write operations to the Boot Block when driven low,
X
regardless of the state of the block lock registers. When TBL is
high it disables hardware write protection for the top Boot Block.
This pin cannot be left unconnected.
LAD[3:0]
LPC Interface I/Os
I/O
X I/O Communications in LPC mode.
LCLK
Clock
IN
X
To provide a clock input to the device. This pin is the same as that
for the PCI clock and adheres to the PCI specifications.
LFRAME
Frame
IN
X
To indicate start of a data transfer operation. LFRAME is also
used to abort an LPC cycle in progress.
RST
Reset
IN X X To reset the operation of the device
WP Write Protect
IN
When low, prevents any write operations to all but the highest
X addressable block. When WP is high it disables hardware write
protection for these blocks. This pin cannot be left unconnected.
R/C
Row/Column Select IN
X
This pin determines whether the address pins are pointing to the
row addresses or the column addresses in A/A Mux mode.
R/B
Ready/Busy
OUT X
This pin is used to determine if the device is busy in write
operations. Valid only in A/A Mux mode.
RES
Reserved
X Reserved. These pins must be left unconnected.
VDD
Power Supply
PWR X
X To provide power supply (3.0-3.6Volt).
VSS
Ground
PWR X
X Circuit ground. All VSS pins must be grounded.
NC No Connection
X X Unconnected pins.
Notes: IN=Input, OUT=output, I/O=Input/Output, PWR=Power
PRELIMINARY (March, 2006, Version 0.1)
4
AMIC Technology, Corp.
5 Page 
A49LF040A
Table 5: Address Decoding Range
ID Strapping
Device #0 – 7
Device #8 - 15
Device Access
Memory Access
Register Access
Memory Access
Register Access
A21:A19
FFFF FFFFH: FFC0 0000H
FFBF FFFFH: FF80 0000H
FF7F FFFFH: FF40 0000H
FF3F FFFFH: FF00 0000H
Memory Size
4 MByte
4 MByte
4 MByte
4 MByte
Table 6: Multiple Device Selection Configurations
Device#
0 (Boot device)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Hardware Strapping
ID[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A23
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Address Bits Decoding
A21 A20
11
11
10
10
01
01
00
00
11
11
10
10
01
01
00
00
A19
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Table 7: LPC Register Memory Map (Boot Device)
Memory
Address
FFBF0002h
FFBE0002h
FFBD0002h
FFBC0002h
FFBB0002h
FFBA0002h
FFB90002h
FFB80002h
FFBC0100h
FFBC0000h
FFBC0001h
FFBC0003h
Mnemonic
T_BLOCK_LK
T_MINUS01_LK
T_MINUS02_LK
T_MINUS03_LK
T_MINUS04_LK
T_MINUS05_LK
T_MINUS06_LK
T_MINUS07_LK
GPI_REG
MANUF_REG
DEV_REG
CONT_REG
Register Name
Top Block Lock Register (Block 7)
Top Block [-1] Lock Register (Block 6)
Top Block [-2] Lock Register (Block 5)
Top Block [-3] Lock Register (Block 4)
Top Block [-4] Lock Register (Block 3)
Top Block [-5] Lock Register (Block 2)
Top Block [-6] Lock Register (Block 1)
Top Block [-7] Lock Register (Block 0)
LPC General Purpose Input Register
Manufacturer ID Register
Device ID Register
Continuation ID Register
Default
01h
01h
01h
01h
01h
01h
01h
01h
N/A
37h
9Dh
7Fh
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
PRELIMINARY (March, 2006, Version 0.1)
10
AMIC Technology, Corp.
11 Page | ||
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