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ispPAC-POWR6AT6 の電気的特性と機能

ispPAC-POWR6AT6のメーカーはLattice Semiconductorです、この部品の機能は「In-System Programmable Power Supply Monitoring and Margining Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 ispPAC-POWR6AT6
部品説明 In-System Programmable Power Supply Monitoring and Margining Controller
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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ispPAC-POWR6AT6 Datasheet, ispPAC-POWR6AT6 PDF,ピン配置, 機能
www.DataSheet4U.com
ispPAC-® POWR6AT6
In-System Programmable Power Supply
Monitoring and Margining Controller
April 2006
Preliminary Data Sheet
Features
Application Block Diagram
Power Supply Margin and Trim Functions
• Trim and margin up to six power supplies
• Dynamic voltage control through I2C
• Four hardware selectable voltage profiles
• Independent Digital Closed-Loop Trim function
for each output
Analog Input Monitoring
• Six analog monitor inputs
• Differential input architecture for accurate
remote ground sensing
• 10-bit ADC for direct voltage measurements
2-Wire (I2C/SMBus™ Compatible) Interface
• Readout of the ADC
• Dynamic trimming/margining control
Other Features
• Programmable analog circuitry
• Wide supply range, 2.8V to 3.96V
• In-system programmable through JTAG
• Industrial temperature range: -40°C to +85°C
• 32-pin QFN package, only 5mm x 5mm, lead-
free option
Description
3.3V
2.5V
1.8V
POL#1
POL#2
POL#3
Vout
Trim
Vout
Trim
Vout
Trim
Vout
Trim
Vout
Trim
Vout
Trim
6 Analog
Trim Outputs
Power Supply
Margin/Trim
Control
6 Analog
Monitor Inputs
ADC
I2 C
Interface
CPU
I2C
Bus
Lattice’s Power Manager II ispPAC-POWR6AT6 is a
general-purpose power-supply monitoring and margin-
ing controller, incorporating in-system programmable
analog functions implemented in non-volatile E2CMOS®
technology. The ispPAC-POWR6AT6 device provides
six independent analog input channels to monitor up to
six power supply test points. Each of these input chan-
nels offers a differential input to support remote ground
sensing.
The ispPAC-POWR6AT6 incorporates six DACs for gen-
erating a trimming voltage to control the output voltage
of a power supply. The trimming voltage can be set to
four hardware selectable preset values (voltage profiles)
or can be dynamically loaded in to the DAC through the
I2C bus. Additionally, each power supply output voltage
can be maintained typically within 0.5% tolerance
across various load conditions using the Digital Closed
Loop Control mode. The operating voltage profile can
be selected using external hardware pins.
ispPAC-POWR6AT6
The on-chip 10-bit A/D converter can both be used to
monitor the VMON voltage through the I2C bus as well as
for implementing digital closed loop mode for maintain-
ing the output voltage of all power supplies controlled by
the monitoring and trimming section of the ispPAC-
POWR6AT6 device.
The I2C bus/SMBus interface allows an external micro-
controller to measure the voltages connected to the
VMON analog monitor inputs and load the DACs for the
generation of the trimming voltages of the external DC-
DC converters.
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
1
6at6_01.0

1 Page





ispPAC-POWR6AT6 pdf, ピン配列
Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Pin Descriptions
Number
7
8
6
Name
VPS0
VPS1
CLTENb
Pin Type
Digital Input
Digital Input
Digital Input
9
CLTLOCK/
SMBA
Open Drain Output1
15 VMON1
Analog Input
14 VMON1GS Analog Input
17 VMON2
Analog Input
16 VMON2GS Analog Input
19 VMON3
Analog Input
18 VMON3GS Analog Input
21 VMON4
Analog Input
20 VMON4GS Analog Input
23 VMON5
Analog Input
22 VMON5GS Analog Input
25 VMON6
Analog Input
24 VMON6GS Analog Input
32 GND
Ground
12 VCCD4
Power
13 VCCA4
Power
2 VCCJ
Power
31 TRIM1
Analog Output
30 TRIM2
Analog Output
29 TRIM3
Analog Output
28 TRIM4
Analog Output
27 TRIM5
Analog Output
26 TRIM6
Analog Output
Voltage Range
VCCD
VCCD
VCCD
0V to 5.5V
-0.3V to 5.75V
-0.3V to 0.3V3
-0.3V to 5.75V
-0.3V to 0.3V3
-0.3V to 5.75V
-0.3V to 0.3V3
-0.3V to 5.75V
-0.3V to 0.3V3
-0.3V to 5.75V
-0.3V to 0.3V3
-0.3V to 5.75V
-0.3V to 0.3V3
Ground
2.8V to 3.96V
2.8V to 3.96V
2.25V to 3.6V
-320mV to +320mV
from Programmable
DAC Offset
-320mV to +320mV
from Programmable
DAC Offset
-320mV to +320mV
from Programmable
DAC Offset
-320mV to +320mV
from Programmable
DAC Offset
-320mV to +320mV
from Programmable
DAC Offset
-320mV to +320mV
from Programmable
DAC Offset
Description
Trim Select Input 0
Trim Select Input 1
Enables closed loop trim process (asserted
low)
Signals that all TrimCells selected for closed-
loop trim have reached a trim locked condi-
tion. Can be configured to be compliant with
SMBus Alert protocol.2
Voltage Monitor 1 Input
Voltage Monitor 1 Ground Sense
Voltage Monitor 2 Input
Voltage Monitor 2 Ground Sense
Voltage Monitor 3 Input
Voltage Monitor 3 Ground Sense
Voltage Monitor 4 Input
Voltage Monitor 4 Ground Sense
Voltage Monitor 5 Input
Voltage Monitor 5 Ground Sense
Voltage Monitor 6 Input
Voltage Monitor 6 Ground Sense
Ground
Core VCC, Main Power Supply
Analog Power Supply
VCC for JTAG Logic Interface Pins
Trim DAC Output 1
Trim DAC Output 2
Trim DAC Output 3
Trim DAC Output 4
Trim DAC Output 5
Trim DAC Output 6
3


3Pages


ispPAC-POWR6AT6 電子部品, 半導体
Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Margin/Trim DAC Output Characteristics
Symbol
Parameter
Conditions
Min Typ Max Units
Resolution
8(7+sign)
bits
FSR
Full scale range
+/-320
mV
LSB LSB step size
2.5 mV
IOUT
Output source/sink current
Offset 1
-125
125 µA
0.6
VBPZ
Bipolar zero output voltage
(code=80h)
Offset 2
Offset 3
0.8
V
1.0
Offset 4
1.25
DAC code changed
from 80H to FFH or
TS
TrimCell output voltage settling
time1
80H to 00H
Single DAC code
change
2.5 ms
256 µs
C_LOAD
Maximum load capacitance
50 pF
TUPDATEM
TOSE
Update time through I2C port2
Total open loop supply voltage
error3
Full scale DAC corre-
sponds to ±5% supply
voltage variation
-0.75
260
+0.75
µs
%
1. To 1% of set value with 50pf load connected to trim pins.
2. Total time required to update a single TRIMx output value by setting the associated DAC through the I2C port.
3. This is the total resultant error in the trimmed power supply output voltage referred to any DAC code due to the DAC’s INL, DNL, gain, out-
put impedance, offset error and bipolar offset error across the industrial temperature range and the ispPAC-POWR6AT6 operating VCCA
and VCCD ranges.
ADC Characteristics
Symbol
Parameter
Conditions
Min. Typ.
ADC resolution
10
Programmable attenuator = 1
VIN Input range full scale
Programmable attenuator = 3
0
0
TCONVERT
Conversion complete time
Time from I2C request to complete one
conversion cycle
ADC Step Size LSB
Programmable attenuator = 1
Programmable attenuator = 3
2
6
Eattenuator Error due to attenuator
Programmable attenuator = 3
+/- 0.1
1. Maximum voltage is limited by VMONX pin (theoretical maximum is 6.144V).
2. Minimum time to wait for valid ADC result. Applies when not reading the DONE status bit (via I2C) to determine ADC.
Max.
2.048
5.751
2002
Units
Bits
V
V
µs
mV
mV
%
ADC Error Budget Across Entire Operating Temperature Range
Symbol
Parameter
Conditions
Min.
Measurement Range 600 mV to 2.048V,
VMONxGS > -100mV, Attenuator =1
-8
TADC Error
Total Measurement Error at Measurement Range 600 mV to 2.048V,
Any Voltage1
VMONxGS > -200mV, Attenuator =1
Measurement Range 0 to 2.048V,
VMONxGS > -200mV, Attenuator =1
1. Total error, guaranteed by characterization, includes INL, DNL, Gain, Offset, and PSR specs of the ADC.
Typ.
+/-4
+/-6
+/-10
Max.
8
Units
mV
mV
mV
6

6 Page



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部品番号部品説明メーカ
ispPAC-POWR6AT6

In-System Programmable Power Supply Monitoring and Margining Controller

Lattice Semiconductor
Lattice Semiconductor


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