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Número de pieza | IRPP3624-12A | |
Descripción | Single Phase Synchronous Buck POWER+ Chipset Reference Design | |
Fabricantes | International Rectifier | |
Logotipo | ||
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IRPP3624-12A POWIR+ Chipset
Reference Design #0612
12Amp Single Phase Synchronous Buck
POWIR+TM Chipset Reference Design
using IR3624MPBF PWM & Driver IC and IRF7823
and IRF7832Z MOSFET
By Steve Oknaian, Senior Applications Engineer
www.irf.com
RD#0612
1
1 page www.DataSheet4U.com
Layout Considerations
The IRPP3624-12A reference design
PCB layout offers compact design with
minimum parasitics at 600kHz switching
frequency. The board is designed with
4 layers using 1 oz copper weight per
layer. Figures 3a through 3d represent
the layout of each layer. To minimize
the parasitics, the following was
observed:
1. The switch node connection path is
made as short as possible by placing
the output inductor L1 close to the drain
of the synchronous FET.
2. The input decoupling 10uF ceramic
capacitors C1 through C4, are placed
across the drain of the control FET and
the PGND/
3. A solid ground plane is furnished in
mid-layer 2. The connection of the
signal ground to power ground is done
at a single point in the bottom layer as
shown in figure 3d.
4. The feedback track from the output
VOUT to FB pin of the IC is routed as far
away from noise generating traces as
possible in mid-layer 2 as shown in
figure 3c.
www.irf.com
RD#0612
5
5 Page www.DataSheet4U.com
Figure 5: IRPP3624-12A Reference Design Thermograph at 12A load
Phase Plot,
Phmargin=73
Gain Plot,
F0=64kHz
Figure 6: IRPP3624-12A Reference Design Bode Plot of the Control Loop at 12A load.
www.irf.com
11
RD#0612
11 Page |
Páginas | Total 15 Páginas | |
PDF Descargar | [ Datasheet IRPP3624-12A.PDF ] |
Número de pieza | Descripción | Fabricantes |
IRPP3624-12A | Single Phase Synchronous Buck POWER+ Chipset Reference Design | International Rectifier |
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