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PDF ISP1506B Data sheet ( Hoja de datos )
| Número de pieza | ISP1506B | |
| Descripción | (ISP1506A/B) ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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ISP1506A; ISP1506B
ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver
Rev. 01 — 30 May 2007
Product data sheet
1. General description
The ISP1506 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully
compliant with Ref. 1 “Universal Serial Bus Specification Rev. 2.0”, Ref. 2 “On-The-Go
Supplement to the USB 2.0 Specification Rev. 1.2” and Ref. 3 “UTMI+ Low Pin Interface
(ULPI) Specification Rev. 1.1”.
The ISP1506 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer
front-end attachment to USB host, peripheral and OTG devices.
It is ideal for use in portable electronic devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) and any system chip set to interface with the physical layer of the
USB through an 8-pin interface.
The ISP1506 can interface to devices with digital I/O voltages in the range of 1.65 V to
1.95 V.
The ISP1506 is available in HVQFN24 package.
2. Features
I Fully complies with:
N Ref. 1 “Universal Serial Bus Specification Rev. 2.0”
N Ref. 2 “On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2”
N Ref. 3 “UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1”
I Interfaces to host, peripheral and OTG device cores; optimized for portable devices or
system ASICs with built-in USB OTG device core
I Complete Hi-Speed USB physical front-end solution that supports high-speed
(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
N Integrated 45 Ω ± 10 % high-speed termination resistors, 1.5 kΩ ± 5 % full-speed
device pull-up resistor, and 15 kΩ ± 5 % host termination resistors
N Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
N USB clock and data recovery to receive USB data at ±500 ppm
N Insertion of stuff bits during transmit and discarding of stuff bits during receive
N Non-Return-to-Zero Inverted (NRZI) encoding and decoding
N Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
I Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP)
1 page  
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NXP Semiconductors
6. Pinning information
6.1 Pinning
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
terminal 1
index area
VCC(I/O)
RREF
DM
DP
ID
CPGND
1
2
3
4
5
6
ISP1506
18 NXT
17 STP
16 DIR
15 REG1V8
14 RESET_N/PSW_N
13 XTAL2
004aaa599
Transparent top view
Fig 2. Pin configuration HVQFN24
6.2 Pin description
Table 2. Pin description
Symbol[1][2][3] Pin
Type[4]
VCC(I/O)
RREF
1P
2 AI/O
DM 3 AI/O
DP 4 AI/O
ID 5 I
CPGND
C_B
C_A
VCC
VBUS/FAULT
6
7
8
9
10
P
AI/O
AI/O
P
AI/O
REG3V3
XTAL1
XTAL2
11 P
12 AI
13 AO
Description
I/O supply rail
resistor reference
data minus (D−) pin of the USB cable
data plus (D+) pin of the USB cable
identification (ID) pin of the mini-USB cable
If this pin is not used, it is recommended to connect it to REG3V3.
plain input; TTL level
charge pump ground
flying capacitor pin connection for the charge pump
flying capacitor pin connection for the charge pump
input supply voltage or battery source
This pin has two possible functions:
VBUS (analog input and output) — VBUS pin of the USB cable
FAULT (input) — Input pin for the external VBUS digital overcurrent or fault detector
signal
If this pin is not used as either VBUS or FAULT, it must be connected to ground.
plain input; 5 V tolerant
3.3 V regulator output
crystal oscillator or clock input
crystal oscillator output
ISP1506A_ISP1506B_1
Product data sheet
Rev. 01 — 30 May 2007
© NXP B.V. 2007. All rights reserved.
5 of 79
5 Page 
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NXP Semiconductors
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
7.9.3 RREF
Resistor reference analog I/O pin. A resistor, RRREF, must be connected between RREF
and GND, as shown in Section 16. This provides an accurate voltage reference that
biases internal analog circuitry. Less accurate resistors cannot be used and will render the
ISP1506 unusable.
7.9.4 DP and DM
DP (data plus) and DM (data minus) are USB differential data pins. These must be
connected to the D+ and D− pins of the USB receptacle.
7.9.5 ID
For OTG implementations, the ID (identification) pin is connected to the ID pin of the
mini-USB receptacle. As defined in Ref. 2 “On-The-Go Supplement to the USB 2.0
Specification Rev. 1.2”, the ID pin dictates the initial role of the link. If ID is detected as
HIGH, the link must assume the role of a peripheral. If ID is detected as LOW, the link
must assume a host role. Roles can be swapped at a later time by using HNP.
If the ISP1506 is not used as an OTG PHY, but as a standard USB host or peripheral PHY,
the ID pin must be connected to REG3V3.
7.9.6 CPGND
CPGND indicates the analog ground for the on-board charge pump. CPGND must always
be connected to ground, even when the charge pump is not used.
7.9.7 C_A and C_B
The C_A and C_B pins are to connect the flying capacitor of the charge pump. The output
current capability of the charge pump depends on the value of the capacitor used, as
shown in Table 3. For maximum efficiency, place capacitors as close as possible to pins.
For details, see Section 16.
If the charge pump is not used, C_A and C_B must be left floating (not connected).
C_A
C_B
ISP1506
VBUS
Fig 4. Charge pump capacitor
Ccp(C_A)-(C_B)
IL
004aaa601
Table 3. Recommended charge pump capacitor value
Ccp(C_A)-(C_B)
22 nF
IL (max)
8 mA
270 nF
50 mA
ISP1506A_ISP1506B_1
Product data sheet
Rev. 01 — 30 May 2007
© NXP B.V. 2007. All rights reserved.
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