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HI3197 の電気的特性と機能

HI3197のメーカーはIntersil Corporationです、この部品の機能は「125 MSPS D/A Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 HI3197
部品説明 125 MSPS D/A Converter
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HI3197 Datasheet, HI3197 PDF,ピン配置, 機能
Data Sheet
HI3197
October 1998 File Number 4356.1
10-Bit, 125 MSPS D/A Converter
The HI3197 is a high-speed D/A converter which can
perform the multiplexed input of the two system 10-bit data.
The maximum conversion rate achieves 125 MSPS. The
multiplexed operation is possible by the 1/2 frequency-
divided clock or by halving the frequency of the clock with
the clock frequency divider circuit having the reset pin in
the IC. The data input is TTL; the clock input pin and reset
input pin can select either TTL or PECL according to the
application.
Ordering Information
PART NUMBER
HI3197JCQ
TEMP.
RANGE (oC) PACKAGE
-20 to 75 48 Ld MQFP/
PQFP
PKG. NO.
Q48.7x7-S
Features
• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bits
• Conversion Rate
125 MSPS (PECL)
100 MSPS (TTL)
• Data Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TTL
• Low Power Consumption . . . . . . . . . . . . . . . 400mW (Typ)
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . 1.5pV•s
• Clock, Reset Input Level: TTL and PECL Compatible 2:1
Multiplexed Input Function
1/2 Frequency-Divided Clock Output Possible by the Built-
In Clock Frequency Divider Circuit
• Voltage Output (50Load Drive Possible)
• Single Power Supply or ±Dual Power Supplies
• Polarity Switching Function of Reset Signal
Applications
• LCD
• DDS
• HDTV
• Communications (QPSK, QAM)
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Pinout
HI3197 (MQFP)
TOP VIEW
AGND2
VOCLP
R POLARITY
INV
PS
DVCC1
NC
DGND1
(MSB) DA9
DA8
DA7
DA6
36 35 34 33 32 31 30 29 28 27 26 25
37 24
38 23
39 22
40 21
41 20
42 19
43 18
44 17
45 16
46 15
47 14
48 13
1 2 3 4 5 6 7 8 9 10 11 12
RESETN/E
RESETP/E
RESET/T
CLKN/E
CLKP/E
CLK/T
DIV2OUT
DIV2IN
DB0 (LSB)
DB1
DB2
DB3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

1 Page





HI3197 pdf, ピン配列
HI3197
Pin Descriptions and I/O Pin Equivalent Circuits
PIN NO
1 to 6
45 to 48
7 to 16
SYMBOL
DA0 to DA9
DB0 to DA9
TYPICAL
VOLTAGE
I/O LEVEL
I TTL
I TTL
EQUIVALENT CIRCUIT
DVCC1
1 TO 6
45 TO 48
7 TO 16
17
DIV2IN
I TTL
DGND1
DVCC1
DESCRIPTION
Side A Data Input.
Side B Data Input.
VREF
1/2 Frequency-Divided Clock Input.
Use this pin for MUX.1A or MUX.2
mode. Leave open for other modes.
17 VREF
18 DIV2OUT O TTL
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19
CLK/T
I TTL
DGND1
DVCC1
19
DVCC1
18
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Out-
fre-
quency divided clock (DIV2OUT) is
output for MUX.1A mode. Leave
open for other modes.
DGND1
Clock Input. Use this pin when the
clock is input in the TTL level. At
this time, leave Pins 20 and 21
open.
VREF
20
CLKP/E
I PECL
21
CLKN/E
I PECL
DGND1
DVCC1
20
21
DGND1
Clock Input. Use this pin when the
clock is input in PECL level. At this
time, leave Pin 19 open.
CLKP/E Complementary Input.
When left open, this pin goes to
the threshold potential. Operation
is possible only with CLKP/E, but
complementary input is recom-
mended to attain fast and stable
operation.
3


3Pages


HI3197 電子部品, 半導体
HI3197
Pin Descriptions and I/O Pin Equivalent Circuits (Continued)
PIN NO
40
SYMBOL
INV
TYPICAL
VOLTAGE
I/O LEVEL
I TTL
DVCC1
EQUIVALENT CIRCUIT
DESCRIPTION
Analog Output polarity inversion.
The analog output is inverted at low
level.
41 PS I TTL
40
DGND1
DVCC1
41
VREF
Power saving. Power saving at low
level. Normally pull up the PS pin
to high level as this pin is open low.
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42
43
44
DVCC1
NC
DGND1
5V
0V
DGND1
Digital Power Supply.
No connection.
Digital Ground.
6

6 Page



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共有リンク

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部品番号部品説明メーカ
HI3197

125 MSPS D/A Converter

Intersil Corporation
Intersil Corporation


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