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PDF IA82527 Data sheet ( Hoja de datos )
| Número de pieza | IA82527 | |
| Descripción | Serial Communications Controller CAN Protocol | |
| Fabricantes | InnovASIC | |
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IA82527
CAN Serial Communications Controller
As of Production Ver. 00
04 May 2007
PRELIMINARY
IA82527
Serial Communications Controller ▪ CAN Protocol
Data Sheet
www.DataSheet4U.com
Document Version 1.0
Copyright 2007
©
EN21070504-00
Page 1 of 45
www.Innovasic.com
Customer Support:
1-888-824-4184
1 page  
IA82527
CAN Serial Communications Controller
As of Production Ver. 00
04 May 2007
PRELIMINARY
1. Introduction
The Innovasic Semiconductor IA82527 Controller Area Network (CAN) Serial Communications
Controller is a form, fit, and function replacement for the original Intel® 82527 Serial
Communications Controller.
These devices are produced using Innovasic’s Managed IC Lifetime Extension System
(MILES™). This cloning technology, which produces replacement ICs beyond simple
emulations, ensures complete compatibility with the original device, including any
“undocumented features.” Additionally, MILES™ captures the clone design in such a way that
production of the clone can continue even as silicon technology advances.
The IA82527 Serial Communications Controller replaces the obsolete Intel® 82527 device,
allowing users to retain existing board designs, software compilers/assemblers, and emulation
tools, thereby avoiding expensive redesign efforts.
NOTE
This data sheet contains preliminary information for the
Innovasic Semiconductor IA82527 Serial Communications
Controller. The finalized data sheet that documents all
necessary engineering information about the IA82527 will be
available when the device nears completion in Q2 2008.
1.1 General Description
Controller Area Network (CAN) protocol uses a multi-master CSMA/CR (Carrier Sense, Multiple
Access with Collision Resolution) bus to transfer message objects between network nodes.
The IA82527 supports CAN Specification 2.0 Part A and B, standard and extended message
frames, and has the capability to transmit, receive, and perform message filtering on extended
message frames.
The IA82527 can store 15 message objects of 8-byte data length. Each message object can be
configured as either transmit or receive except for the last message object, which is receive-
only. The last message object also provides a special acceptance mask designed to allow
select groups of different message identifiers to be received.
The IA82527 also provides a programmable acceptance mask that allows users to globally
mask any identifier bits of the incoming message. This global mask can be used for both
standard and extended message frames.
Copyright 2007
©
EN21070504-00
Page 5 of 45
www.Innovasic.com
Customer Support:
1-888-824-4184
5 Page 
IA82527
CAN Serial Communications Controller
As of Production Ver. 00
04 May 2007
PRELIMINARY
Table 3. IA82527 Pin/Signal Descriptions, continued
Signal
Name
Pin
PLCC
QFP
as ale/as
5 43
clkout
— 27 21
cp a1/ad1/cp
3 41
cs_n
— 82
csas
d0
d1
d2
d3
d4
d5
d6
d7
a2/ad2/csas
ad8/d0/p1.0
ad9/d1/p1.1
ad10/d2/p1.2
ad11/d3/p1.3
ad12/d4/p1.4
ad13/d5/p1.5
ad14/d6/p1.6
ad15/d7/p1.7
2 40
38 32
37 31
36 30
35 29
34 28
33 27
32 26
31 25
Description
address strobe. Input. Active High. Mode 2.
When the IA82527 is configured to operate in either the 8-bit
multiplexed non-Intel® architecture mode (Mode 2), this signal latches
the address into the device during the address phase of the bus
cycle.
NOTE: If the IA82527 is configured to operate in Mode 3 (8-bit non-
multiplexed non-Intel® architecture), this pin must be tied high.
clock out. Output (push-pull).
This output provides a programmable clock frequency. The
frequency is set via the Clockout Register (1FH) and can range from
the frequency of the xtal (crystal) input to xtal/n, where n can be an
integer value from 2 through 15. This output allows the IA82527 to
clock other devices such as the host CPU.
clock phase. Input. Serial Interface Mode.
When this input is a logic 0, data are sampled on the rising edge of
sclk. When this input is a logic 1, data are sampled on the falling
edge of sclk.
chip select. Input. Active Low (Modes 0–3); Selectable Active Level
(Serial Interface Mode).
When the IA82527 is configured to operate in one of the parallel
interface modes (Modes 0–3) or the Serial Interface Mode, this input,
during its active state, selects the device allowing CPU access.
For Serial Interface Mode operation, the active state is selectable
(i.e., either high or low) via the IA8257 csas pin.
chip select active state. Input. Serial Interface Mode.
When this input is a logic 0, the cs_n input is configured to function
active low. When this input is a logic 1, the cs_n input is configured
to function active high.
data bits 7–0. Input/Output. Mode 3.
When the IA82527 is configured to operate in the 8-bit non-
multiplexed non-Intel® architecture mode (Mode 3), these lines
provide the 8-bit data bus to the device.
continued . . .
Copyright 2007
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EN21070504-00
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11 Page | ||
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