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3D7701 の電気的特性と機能

3D7701のメーカーはData Delay Devicesです、この部品の機能は「MONOLITHIC GATED DELAY LINE OSCILLATOR」です。


製品の詳細 ( Datasheet PDF )

部品番号 3D7701
部品説明 MONOLITHIC GATED DELAY LINE OSCILLATOR
メーカ Data Delay Devices
ロゴ Data Delay Devices ロゴ 




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3D7701 Datasheet, 3D7701 PDF,ピン配置, 機能
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MONOLITHIC GATED
DELAY LINE OSCILLATOR
(SERIES 3D7701)
3D7701
FEATURES
All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Frequency range: 0.3MHz through 100MHz
Frequency tolerance: 0.5% typical
Temperature stability: ±1.5% typical (-40C to 85C)
Vdd stability: ±0.5% typical (4.75V to 5.25V)
14-pin DIP available as drop-in replacements for
hybrid delay line oscillator (DLO31F)
PACKAGES
O1
NC
NC
GND
18
27
36
45
VDD
NC
O2
EN
3D7701Z-xx SOIC-8
O1
NC
NC
NC
NC
NC
GND
3D7701-xx
3D7701K-xx
1 14 VDD
2 13 NC
3 12 NC
4 11 NC
5 10 O2
6 9 NC
7 8 EN
DIP-14
NC pins removed
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7701 Delay Line Oscillator product family consists of fixed-
EN Oscillator Enable
frequency CMOS integrated circuit oscillators. Each package contains a
O1 Oscillator Output 1
single oscillator, which is gated and can therefore be synchronized to an
O2 Oscillator Output 2
external signal. The device frequency can range from 0.3MHz through
VDD +5 Volts
100MHz. The 3D7701 has two outputs that are in phase when the
GND Ground
oscillator is running, and can be used as a drop-in replacement for the
DLO31F hybrid oscillator. The 3D7701 is TTL- and CMOS-compatible, capable of driving ten 74LS-type
loads. It is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC
package.
NOTE:
TABLE 1: PART NUMBER SPECIFICATIONS
DASH
NUMBER
-0.3
-0.4
-0.5
-0.75
-1
-2
-2.5
-3
-4
-5
-7.5
-10
-20
-25
-30
-40
-50
-75
-100
OUTPUT FREQUENCY (MHz)
25C -40C to 85C
Vdd=5.00V 4.75<Vdd<5.25
0.3 ± 0.002
0.3 ± 0.008
0.4 ± 0.002
0.4 ± 0.010
0.5 ± 0.003
0.5 ± 0.013
0.75 ± 0.004
0.75 ± 0.019
1.0 ± 0.005
1.0 ± 0.025
2.0 ± 0.010
2.0 ± 0.050
2.5 ± 0.013
2.5 ± 0.063
3.0 ± 0.015
3.0 ± 0.075
4.0 ± 0.020
4.0 ± 0.100
5.0 ± 0.025
5.0 ± 0.125
7.5 ± 0.038
7.5 ± 0.188
10.0 ± 0.05
10.0 ± 0.25
20.0 ± 0.10
20.0 ± 0.50
25.0 ± 0.13
25.0 ± 0.63
30.0 ± 0.15
30.0 ± 0.75
40.0 ± 0.20
40.0 ± 1.00
50.0 ± 0.25
50.0 ± 1.25
75.0 ± 0.38
75.0 ± 3.75
100.0 ± 0.50
100.0 ± 7.00
Any dash number between 0.3 and 100 not shown is also available as standard.
2006 Data Delay Devices
Doc #06023
12/5/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1

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3D7701 pdf, ピン配列
3D7701
APPLICATION NOTES (CONT’D)
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7701 oscillator utilizes novel
and innovative compensation circuitry to
minimize the frequency variations induced by
fluctuations in power supply and/or temperature.
The thermal coefficient is reduced to 250 PPM/C,
which is equivalent to a variation, over the -40C
to 85C operating range, of ±1.5% from the room-
temperature frequency setting. The power supply
coefficient is reduced, over the 4.75V to 5.25V
operating range, to ±0.5% of the frequency
setting at the nominal 5.0VDC power supply.
These specifications hold for the lower
frequencies only. For higher dash numbers, the
variations will be slightly greater, as noted in
Table 1. It is essential that the power supply
pin be adequately bypassed and filtered. In
addition, the power bus should be of as low
an impedance construction as possible.
Power planes are preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL MIN
MAX UNITS NOTES
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
VDD
VIN
IIN
TSTRG
TLEAD
-0.3 7.0 V
-0.3 VDD+0.3 V
-1.0 1.0 mA 25C
-55 150 C
300 C 10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output
Current
Low Level Output Current
SYMBOL
IDD
VIH
VIL
IIH
IIL
IOH
IOL
Output Rise & Fall Time
TR & TF
MIN
2.0
4.0
TYP
3.5
-35.0
15.0
2.0
MAX
5.5
0.8
1.0
1.0
-4.0
2.5
UNITS
mA
V
V
µA
µA
mA
mA
ns
NOTES
VIH = VDD
VIL = 0V
VDD = 4.75V
VOH = 2.4V
VDD = 4.75V
VOL = 0.4V
CLD = 5 pf
*IDD(Dynamic) = 2 * CLD * VDD * F
where: CLD = Average capacitance load/output (pf)
F = Device frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
Doc #06023
12/5/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3


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部品番号部品説明メーカ
3D7701

MONOLITHIC GATED DELAY LINE OSCILLATOR

Data Delay Devices
Data Delay Devices


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