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3D3424 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 3D3424
部品説明 MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE
メーカ Data Delay Devices
ロゴ Data Delay Devices ロゴ 

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3D3424 Datasheet, 3D3424 PDF,ピン配置, 機能
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MONOLITHIC QUAD 4-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D3424)
3D3424
FEATURES
Four indep’t programmable lines on a single chip
All-silicon CMOS technology
Low quiescent current (5mA typical)
Leading- and trailing-edge accuracy
Vapor phase, IR and wave solderable
Increment range: 1ns through 300ns
Delay tolerance: 3% or 2ns (see Table 1)
Line-to-line matching: 1% or 1ns typical
Temperature stability: ±1.5% typical (-40C to 85C)
Vdd stability: ±0.5% typical (3.0V to 3.6V)
Minimum input pulse width: 10% of total delay
PACKAGES
I1
SC
I2
I3
I4
SI
GND
1 14
2 13
3 12
4 11
5 10
69
78
DIP-14
3D3424-xx
VDD
AL
O1
SO
O2
O3
O4
I1
SC
I2
I3
I4
SI
GND
1 14 VDD
2 13 AL
3 12 O1
4 11 SO
5 10 O2
6 9 O3
7 8 O4
SOIC-14
3D3424D-xx
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D3424 device is a small, versatile, quad 4-bit programmable
I1-I4 Signal Inputs
monolithic delay line. Delay values, programmed via the serial interface,
O1-O4 Signal Outputs
can be independently varied over 15 equal steps. The step size (in ns) is
AL Address Latch In
determined by the device dash number. Each input is reproduced at the
SC Serial Clock In
corresponding output without inversion, shifted in time as per user
SI Serial Data In
selection. For each line, the delay time is given by:
SO Serial Data Out
TDn = T0 + An * TI
where T0 is the inherent delay, An is the delay address of the n-th line
and TI is the delay increment (dash number). The desired addresses are
VDD 3.3V
GND Ground
shifted into the device via the SC and SI inputs, and the addresses are latched using the AL input. The
serial interface can also be used to enable/disable each delay line. The 3D3424 operates at 3.3 volts and
has a typical T0 of 9ns. The 3D3424 is CMOS-compatible, capable of sourcing or sinking 4mA loads, and
features both rising- and falling-edge accuracy. The device is offered in a standard 14-pin auto-insertable
DIP and a space saving surface mount 14-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
Part
Number
3D3424-1
3D3424-1.5
3D3424-2
3D3424-4
3D3424-5
3D3424-10
3D3424-15
3D3424-20
3D3424-40
3D3424-50
3D3424-100
3D3424-200
3D3424-300
DELAYS & TOLERANCES (NS)
Delay
Step
Inherent
Delay
Total
Delay
Relative
Tolerance
1.0 ± 0.50 9.0 ± 2.0 24.0 ± 2.0 3% or 0.50ns
1.5 ± 0.75 9.0 ± 2.0 31.5 ± 2.0 3% or 0.50ns
2.0 ± 1.00 9.0 ± 2.0 39.0 ± 2.0 3% or 0.75ns
4.0 ± 2.00 9.0 ± 2.0 69.0 ± 2.0 3% or 0.75ns
5.0 ± 2.50 9.0 ± 2.0 84.0 ± 2.5 3% or 0.75ns
10 ± 2.50 9.0 ± 2.0 159 ± 5.0 3% or 1.25ns
15 ± 3.75 9.0 ± 2.0
20 ± 5.00 9.0 ± 2.0
234 ± 7.5 3% or 1.88ns
309 ± 10 3% or 2.50ns
40 ± 10.0 9.0 ± 2.0 609 ± 20 3% or 5.00ns
50 ± 10.0 9.0 ± 2.0 759 ± 25 3% or 6.25ns
100 ± 12.5 9.0 ± 2.0 1509 ± 50 3% or 12.5ns
200 ± 20.0 9.0 ± 2.0 3009 ± 100 3% or 25.0ns
300 ± 30.0 9.0 ± 2.0 4509 ± 150 3% or 37.5ns
INPUT RESTRICTIONS
Max Frequency
Min Pulse Width
Recom’d Absolute Recom’d Absolute
13.8 MHz 166 MHz 36 ns
3.0 ns
10.5 MHz 111 MHz 48 ns
4.5 ns
8.5 MHz 83 MHz
59 ns
6.0 ns
4.8 MHz 41 MHz 104 ns
12.0 ns
4.0 MHz 33 MHz 126 ns
15.0 ns
2.1 MHz 33 MHz 239 ns
15.0 ns
1.4 MHz 22 MHz 351 ns
22.5 ns
1.0 MHz 16 MHz 464 ns
30.0 ns
550 KHz 8.3 MHz 914 ns
60.0 ns
440 KHz 6.6 MHz 1.2 us
75.0 ns
220 KHz 3.3 MHz 2.3 us
150 ns
110 KHz 1.6 MHz 4.5 us
300 ns
74 KHz 1.1 MHz 6.8 us
450 ns
NOTE: Any increment between 1ns and 300ns not shown is also available as standard
See page 4 for details regarding input restrictions
2006 Data Delay Devices
Doc #06020
6/6/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
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