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PDF M2040 Data sheet ( Hoja de datos )
| Número de pieza | M2040 | |
| Descripción | FREQUENCY TRANSLATION PLL | |
| Fabricantes | ICS | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
Product Data Sheet
M2040
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
GENERAL DESCRIPTION
The M2040 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock protection,
frequency translation and jitter
attenuation in fault tolerant
computing applications. It features
dual differential inputs with two
modes of input selection: manual
and automatic upon clock failure. The clock
multiplication ratios and output divider ratio are
pin selectable. External loop components allow the
tailoring of PLL loop response.
FEATURES
◆ Integrated SAW (surface acoustic wave) delay line;
VCSO frequency of 400.00 or 533.3334 MHz;* outputs
VCSO frequency or half; pin-configurable dividers
◆ Loss of Lock (LOL) indicator output
◆ Narrow Bandwidth control input (NBW Pin);
Initialization (INIT) input overrides NBW at power-up
◆ Dual reference clock inputs support LVDS, LVPECL,
LVCMOS, LVTTL
◆ Automatic (non-revertive) reference clock reselection
upon clock failure; controlled PLL slew rate ensures
normal system operation during reference reselection
www.DataSheet4U.com ◆ Acknowledge pin indicates the actively selected
reference input
◆ Dual differential LVPECL outputs
◆ Low phase jitter of < 0.5ps rms, typical
(12kHz to 20MHz or 50kHz to 80MHz)
◆ Industrial temperature available
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
PIN ASSIGNMENT (9 x 9 mm SMT)
FIN_SEL0
MR_SEL
REF_ACK
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30 16
31 M 2 0 4 0 15
32 14
33 ( T o p V i e w ) 13
34 12
35 11
36 10
P_SEL
INIT
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
Example Input / Output Frequency Combinations
Input (MHz) VCSO * (MHz) Output (MHz)
200.0000
213.3333
400.0000
200.0000
400.0000
266.6667
284.4444
533.3334
266.6667
533.3334
Table 1: Example Input / Output Frequency Combinations
* Specify VCSO center frequency at time of order.
Loop Filter
M2040
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
INIT
LOL
MR_SEL
2
FIN_SEL1:0
P_SEL
MUX
0
R Div
1
PLL
Phase
Detector
0
1
Auto
Ref Sel
LOL
Phase
Detector
M / R Divider
LUT
M Div
Mfin Divider
Mfin Divider
LUT
VCSO
P Divider
FOUT0
nFOUT0
FOUT1
nFOUT1
Figure 2: Simplified Block Diagram
M2040 Datasheet Rev 1.0
Revised 28Jan2005
M2040 Frequency Translation PLL with AutoSwitch
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
1 page  
Integrated
Circuit
Systems, Inc.
PLL Operation
The M2040 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
The “M” divider (and the “Mfin” divider) divides the
VCSO output frequency, feeding the result into the plus
input of the phase detector.
The frequency input (“Mfin”) divider gives the device
the capability to be adapted for use with other input
frequencies.
The output of the “R” divider is fed into the minus input
of the phase detector. The phase detector compares its
two inputs. The phase detector output, filtered
externally, causes the VCSO to increase or decrease in
frequency as needed to phase- and frequency-lock the
VCSO to the reference input.
The value of M plus Mfin directly affects closed loop
bandwidth.
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, and the input
reference frequency (Fref_clk) is:
Fvcso = Fref_clk × --M------×------M----f--i--n---
R
The M, R, and Mfin dividers can be set by pin
configuration using the input pins MR_SEL, FIN_SEL1, and
FIN_SEL0.
P Divider and Outputs
The M2040 provides two differential LVPECL output
pairs: FOUT0 and FOUT1. One output divider (the “P”
divider) is used for both the FOUT0 and FOUT1 output
pairs. By using the P divider, the output frequency can
be the VCSO frequency (Fvcso) or 1/2 Fvcso.
The P_SEL pin selects the value for the P divider: logic 1
sets P to divide-by-2, logic 0 sets P to divide-by-1.
See Table 5, P Divider Selector Values
and Frequencies, on pg. 3.
When the P divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
Fout = --F----v---c---s---o---- = Fref_clk × --M------×------M----f--i--n---
P R× P
M2040
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
Product Data Sheet
Loss of Lock Indicator Output Pin
Under normal device operation, when the PLL is locked,
LOL remains at logic 0. Under circumstances when the
VCSO cannot lock to the input (as measured by a
greater than 4 ns discrepancy between the feedback
and reference clock rising edges at the phase detector)
the LOL output goes to logic 1. The LOL pin will return
back to logic 0 when the phase detector error is less
than 2 ns. The loss of lock indicator is a low current
CMOS output.
Narrow Loop Bandwidth Control Pin (NBW Pin)
A Narrow Loop Bandwidth control pin (NBW pin) is
included to adjust the PLL loop bandwidth. In normal
(wide) bandwidth mode (NBW=0), the internal resistor
Rin is 100kΩ. With the NBW pin asserted, the internal
resistor Rin is changed to 2100kΩ. This lowers the loop
bandwidth by a factor of about 21 (2100 / 100) and
lowers the damping factor by about 4.6 (the square root
of 21), assuming the same loop filter components.
M2040 Datasheet Rev 1.0
5 of 12
Revised 28Jan2005
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
5 Page 
Integrated
Circuit
Systems, Inc.
DEVICE PACKAGE - 9 x 9mm SMT CERAMIC
Mechanical Dimensions:
M2040
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
Product Data Sheet
Refer to the M2040 product web page at
www.icst.com/products/summary/m2040.htm
for links to recommended PCB footprint, solder
mask, furnace profile, and related information.
Figure 9: Device Package - 9 x 9mm SMT Ceramic
M2040 Datasheet Rev 1.0
11 of 12
Revised 28Jan2005
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet M2040.PDF ] | |
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