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PDF IRS2004PBF Data sheet ( Hoja de datos )

Número de pieza IRS2004PBF
Descripción HALF-BRIDGE DRIVER
Fabricantes International Rectifier 
Logotipo International Rectifier Logotipo



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No Preview Available ! IRS2004PBF Hoja de datos, Descripción, Manual

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Data Sheet No.PD60270
IRS2004(S)PbF
HALF-BRIDGE DRIVER
Features
Floating channel designed for bootstrap operation
Fully operational to +200 V
Tolerant to negative transient voltage, dV/dt
immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout
3.3 V, 5 V, and 15 V input logic compatible
Cross-conduction prevention logic
Internally set deadtime
High-side output in phase with input
Shutdown input turns off both channels
Matched propagation delay for both channels
RoHS compliant
Product Summary
VOFFSET
200 V max.
IO+/-
130 mA/270 mA
VOUT
10 V - 20 V
ton/off (typ.)
680 ns/150 ns
Deadtime (typ.)
520 ns
Packages
Description
The IRS2004 is a high voltage, high speed power
MOSFET and IGBT driver with dependent high- and low-
side referenced output channels. Proprietary HVIC and
latch immune CMOS technologies enable ruggedized
monolithic construction. The logic input is compatible
8 Lead SOIC
IRS2004S
8 Lead PDIP
IRS2004
with standard CMOS or LSTTL output, down to 3.3 V
logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-
conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side
configuration which operates from 10 V to 200 V.
Typical Connection
up to 200 V
VCC
VCC
VB
IN IN HO
SD SD VS
COM
LO
TO
LOAD
(Refer to Lead Assignment for correct pin configuration). This diagram shows electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
www.irf.com
1

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IRS2004PBF pdf
IRS2004(S) PbF
IN
SD
HO
LO
Figure 1. Input/Output Timing Diagram
IN(LO)
IN(HO)
ton
LO
HO
50%
50%
tr
90%
toff tf
90%
10%
10%
Figure 2. Switching Time Waveform Definitions
SD
50%
tsd
HO 90%
LO
Figure 3. Shutdown Waveform Definitions
IN (LO)
IN (HO)
50%
50%
LO HO
10%
MT MT
90%
LO HO
Figure 5. Delay Matching Waveform Definitions
www.irf.com
50%
IN
50%
90%
HO 10%
DT
LO 90%
DT
10%
Figure 4. Deadtime Waveform Definitions
5

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IRS2004PBF arduino
IRS2004(S) PbF
6
5 Max
4
3
2
1
0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Figure 20A. Logic "0" Input Bias Current
vs. Temperature
11
Max.
10
9 Typ.
Min.
8
7
6
-50 -25
0 25 50 75 100 125
Temperature (°C)
Figure 21A. Vcc Undervoltage Threshold(+)
vs. Temperature
500
400
T yp.
300
200
Min.
100
0
-50 -25 0 25 50 75 100
Temperature (°C)
Figure 22A. Output Source Current
vs. Temperature
125
www.irf.com
6
5 Max
4
3
2
1
0
10 12 14 16 18 20
Supply V oltage (V )
Figure 20B. Logic "0" Input Bias Current
vs. Voltage
11
10
Max.
9
Typ.
8
7 Min.
6
-50 -25 0 25 50 75 100 125
Temperature (°C)
Figure 21B. Vcc Undervoltage Threshold(-)
vs. Temperature
500
400
300
200
T yp.
100
Min.
0
10 12 14 16 18
VBIAS Supply Voltage (V)
Figure 22B. Output Source Current
vs. Voltage
20
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