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PDF AD8156 Data sheet ( Hoja de datos )
| Número de pieza | AD8156 | |
| Descripción | Digital Crosspoint Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD8156 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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6.25 Gbps, 4 × 4,
Digital Crosspoint Switch with EQ
AD8156
FEATURES
4 × 4, fully differential, nonblocking array
Configurable for dual 2 × 2 operation
DC to 6.25 Gbps per channel, NRZ data rate
Programmable input equalization compensates for over 40”
of FR-4 at 6.25 Gbps
Multicast and broadcast modes of operation
Programmable output swing
100 mV p-p to 1.6 V p-p differential
Power supply: 3.3 V (±10%)
Low power
No EQ: 400 mW typical
Maximum EQ: 700 mW typical
Inputs: ac-coupled or dc-coupled
Wide set of dc-coupled input standards
3.3 V/2.5 V/1.8 V CML or 3.3 V LVPECL
Control: LVTTL- or LVCMOS-compatible
Low additive jitter: 25 ps p-p typical
Low random jitter: 0.8 ps rms
Integrated 50 Ω termination impedance at inputs/outputs
Individual output disable for power savings
www.DataSheet4U.com 49-ball, 8 mm × 8 mm BGA, 1 mm pitch
APPLICATIONS
Backplane equalization
SONET/SDH
Gigabit Ethernet
XAUI
Fibre Channel
FUNCTIONAL BLOCK DIAGRAM
IN0P/N
INPUT
RECEIVERS
INPUT
EQUALIZATION
EQ
AD8156
OUTPUT
DRIVERS
OUT0P/N
IN1P/N
IN2P/N
EQ 4 × 4
SWITCH
EQ
OUT1P/N
OUT2P/N
IN3P/N
EQ
OUT3P/N
CS
RST
UPD
WE
RE
MODE
D[3:0]
A[3:0]
4
4
CONTROL
LOGIC
Figure 1.
GENERAL DESCRIPTION
The AD8156, a member of the Xstream line of products, is a
high speed, fully differential, digital crosspoint switch. The part
can function as a 4 × 4 crosspoint switch with double-latched
memory, allowing simultaneous updates, or as a dual 2 × 2 with
direct output control. The AD8156 has low power dissipation,
typically 700 mW on 3.3 V with all outputs and input equalizers
active. It operates at any data rate from dc to 6.25 Gbps per port.
Each input channel on the AD8156 has a programmable input
equalizer to compensate for signal loss over a backplane.
The AD8156 high speed inputs are compatible with both ac-
coupled and dc-coupled 3.3 V, 2.5 V, or 1.8 V CML, as well as
3.3 V LVPECL data levels. The control interface is LVTTL- and
LVCMOS-compatible at 3.3 V. All input and output termination
resistors are integrated for ease of layout and to minimize
impedance mismatch. Input equalization and unused outputs
can be individually disabled to minimize power dissipation.
The AD8156 is packaged in a 49-ball, 8 mm × 8 mm, BGA
package with a 1 mm ball pitch. It operates over the industrial
temperature range of −40°C to 85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
TIMING DIAGRAMS
CS
WE
A[3:0]
D[3:0]
www.DataSheet4U.com
CS
UPD
OUTxN/P
ENABLE
OUTxN/P
DISABLE
OUTxN/P
TOGGLE
tCSW
tASW
tDSW
tWP
tAHW
tCHW
tDHW
Figure 2. First Rank Write Cycle
tCSU
tUOE
tUW
tUOD
tUOT
Figure 3. Second Rank Update Cycle
tCHU
AD8156
Rev. 0 | Page 5 of 20
5 Page 
www.DataSheet4U.com
50
45
40
35
30
25
20
15
10
5
0
3.0 3.1 3.2 3.3 3.4 3.5
VCC (V)
Figure 20. Deterministic Jitter vs. VCC
3.6
50
45
40
35
30
25
20
15
10
5
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT TERMINATION VOLTAGE (V)
Figure 21. Deterministic Jitter vs. Output Termination Voltage
AD8156
800
700
600
500
400
300
200
100
0
0123456789
DATA RATE (Gbps)
Figure 22. Eye Height vs. Data Rate
Rev. 0 | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD8156.PDF ] | |
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