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IS23SC4442 の電気的特性と機能

IS23SC4442のメーカーはISSIです、この部品の機能は「256 BYTE EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS23SC4442
部品説明 256 BYTE EEPROM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS23SC4442 Datasheet, IS23SC4442 PDF,ピン配置, 機能
IS23SC4442
ISSI®
256 BYTE EEPROM
WITH WRITE PROTECT FUNCTION AND
PROGRAMMABLE SECURITY
PRELIMINARY INFORMATION
August 2003
FEATURES
• Standard CMOS process
• 256 x 8 bits EEPROM organization
• Byte-wise addressing
• Irreversible byte-wise write protection of lowest
32 address (Byte 0..31)
• 3-byte Programmable Security Code (PSC) for
memory write/erase protection
• 2.7-5.5V power supply for read and write/erase
• Low power operation: 3 mA typical active current
• 2.5 ms programming time
• 2-wire serial interface
www.DataSheet4U.com
• End of processing indication
• ISO standard 7816 compatible
• High reliability:
1,000,000 erase/write cycles guaranteed
10 years data retention
• Wide operating temperature range
30oC to 75oC
DESCRIPTION
IS23SC4442 contains 256 x 8 bits of EEPROM main
memory and a 32 x 1 bit protection PROM memory.
The main memory can be randomly accessed byte by
byte. During memory erase, all 8 bits of a byte are set
to logical one. During memory write, individual bit(s)
are set to logical zeros depend on the data value to be
written. Normally, a data change may consists of an
erase and a write operation. The write or erase operation
takes at least 2.5 ms to complete.
The first 32 bytes (Address: 0 to 31) in memory are
irreversibly protected by the corresponding 32 protect
bits in the 32 x 1 bit protection memory. The 32 protect
bits are onetime programmable, and they cannot be
erased once they are set to logical zero.
IS23SC4442 provides a 3-bit Error Counter (EC), and
three bytes Programmable Security Code (PSC) to
prevent unauthorized erase/write operation to the
memory. All the memory, except the PSC, can be read
after the chip is powered on. But, the memory can be
written or erased only after the PSC is entered and
verified correct. After three successive unsuccessful
verifications of PSC, the Error Counter locks the chip
from a further attempt, and the memory can never be
erased or written.
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
08/01/03
1

1 Page





IS23SC4442 pdf, ピン配列
IS23SC4442
MEMORY OVERVIEW
ISSI®
VCC
RST
CLK
I/O
GND
Reset,
Blockade
Logic
Interface
Sequencer
and
Security
Logic
Main
Memory
High-Volt
Generator
225
224 Byte
Protection
Memory
(PROM)
Unprotected
Data Memory
32
31 32 Byte
Protectable
Data Memory
Decoder
Manufacturer
0 Code
Functional Description
The IS23SC4442 works on a 2-wire serial transmission
protocol. Data is input or output from the chip through
the I/O pin at the falling edge of CLK. The following are
the four modes of operations:
Reset and Answer-to-Reset
Command Mode
Outgoing Data Mode
Processing Mode
Reset and Answer-to-Reset
The Answer-to-Reset operation conforms to ISO 7816-3
ATR standard. The reset action can be invoked at any
time during the operation to terminate any active com-
mand operation. With RST High, the internal address
counter is set to zero by the CLK pulse. The LSB of the
first byte data in the memory will be output from I/O when
RST goes from High to Low. By continuing to send
pluses to CLK, the contents of the first four bytes will be
output from I/O pin. After the ATR process completes,
the I/O pin will be set to high impedance.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
08/01/03
3


3Pages


IS23SC4442 電子部品, 半導体
IS23SC4442
ISSI®
Command Mode
After Answer-To-Reset, IS23SC4442 waits for a com-
mand entry. Each command begins with a start condi-
tion, which includes a three bytes command entry, and it
ends with a stop condition.
Start condition: during CLK in high level, a falling edge
on I/O
Stop condition: during CLK in high level, a rising edge
on I/O
After receiving a command, there are two possible
modes:
Processing mode for writing and erasing
CLK
I/O
Command
123
1 23
IFD sets I/O
To L-level
23 24
23 24
Start from IFD
Figure: Command Mode
Stop from IFD
Data Output Mode
When reading, the chip sends the data to IFD. The figure
shows the timing diagram. After the first falling edge on
CLK, the first bit on the I/O is valid. After the last data
bit, an additional CLK pulse is necessary to set the I/O
to a high level for receiving a new command. During this
mode, any start and stop condition is ignored.
Command
CLK
I/O
1 23
1 23
IC set I/O
to high-level
n-1
n
n-1 n
Start of output data
Figure: Data Output Mode
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
08/01/03

6 Page



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部品番号部品説明メーカ
IS23SC4442

256 BYTE EEPROM

ISSI
ISSI


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