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ATA6026 の電気的特性と機能

ATA6026のメーカーはATMEL Corporationです、この部品の機能は「H-bridge Motor Driver」です。


製品の詳細 ( Datasheet PDF )

部品番号 ATA6026
部品説明 H-bridge Motor Driver
メーカ ATMEL Corporation
ロゴ ATMEL Corporation ロゴ 




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ATA6026 Datasheet, ATA6026 PDF,ピン配置, 機能
Features
PWM and Direction-controlled Driving of Four Externally Powered NMOS Transistors
Internal Charge Pump Provides Gate Voltages for High-side Drivers in Permanent ON
Mode and Supplies the Gate of the External Battery Reverse Protection NMOS
5V Regulator With External Power Device (NPN) and Current Limitation Function
Reset Derived From 5V Regulator Output Voltage
Sleep Mode With Supply Current of Typical 35 µA, Wake-up by Signal on Pin EN or on
SCI Interface (Pin /DATA)
Window Watchdog; the Watchdog Time is Programmable by Choosing a Certain Value
of the External Watchdog Capacitor CCWD and the External Watchdog Resistor RCWD
Battery Overvoltage Protection and Battery Undervoltage Management
Overtemperature Protection
SCI Transceiver (Operating in Differential or Single-ended Mode) for Use at Battery
Voltage Level
Digital Control Block With the Control Pins EN, DIR, PWM
Internal Low-power Regulator With Low-power Band Gap (Trimmed With Four Bits) to
Guarantee Power Dissipation in Sleep Mode and to Guarantee Parameters for Wake-up
H-bridge Motor
Driver
ATA6026
1. Description
The ATA6026 is used to drive a continuous-current motor in a full H-bridge configura-
tion. An external microcontroller controls the driving function of the ATA6026 by
providingwww.DataSheet4U.com a PWM signal and a direction signal, and allows the usage of the ATA6026
in a windshield wiper application, for example.
The ATA6026 supports PWM and direction-controlled driving of four external power
MOSFETs with two external bootstrap capacitors. The PWM control is performed by
the high-side switch. The opposite low-side switch is permanently ON in the driving
phase. Motor braking is performed using the low-side switches. A programmable dead
time is included to prevent peak currents within the H-bridge. The maximum PWM fre-
quency is 30 kHz.
Rev. 4865C–AUTO–01/06

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ATA6026 pdf, ピン配列
2. Pin Configuration
Figure 2-1. Pinning QFN32
ATA6026
VREG
VSHUNT
VCC
DATA
/DATA
VBAT
CP
PGND
1 2345678
32 9
31 10
30 Atmel YWW 11
29 ATA6026 12
28 ZZZZZ-AL 13
27 14
26 15
25 16
24 23 22 21 20 19 18 17
DG1
DG2
/RESET
RX
TX
WD
CWD
CC
Note:
YWW
ATA6026
ZZZZZ
AL
Date code (Y = Year above 2000, WW = week number)
Product name
Wafer lot number
Assembly sub-lot number
Table 2-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin Description
Symbol
Function
VINT
Supply
GND
VREF
Pin
Analog in
VBAT_SWITCH Analog out (HV)
SEM
Digital input-PU
EN Digital input (HV) PD
PWM
Digital input (HV) PD
DIR
DG1
DG2
/RESET
RX
TX
WD
CWD
Digital input (HV) PD
Digital output
Digital output
Open drain-PU
Digital output-PU
Digital input-PU
Digital input
Analog in/out
Description
Output of internal voltage regulator
(external blocking capacitor)
Ground, substrate of ATA6026
Reference resistor for reference current
Connected with VBAT via an
ATA6026-internal switch
Control of SCI mode (Single-ended Mode)
Enable control input
PWM control input
Direction control input
Status output 1
Status output 2
Reset output, active low
Data output pin of SCI interface
Transmit control input for SCI interface
Watchdog trigger input
Capacitor for definition of watchdog timer
ESD Protection
Open drain 14V
+ diode to GND
+ diode from VCC
Diode to PGND
Open drain 14V
+ diode to GND
Diodes to VBAT/GND
Diodes to GND/VCC
Open drain HV + diode to
GND
Open drain HV + diode to
GND
Open drain HV + diode to
GND
Diodes to GND/VCC
Diodes to GND/VCC
Diodes to GND/VCC
Diodes to GND/VCC
Diodes to GND/VCC
Diodes to GND/VCC
Diodes to GND/VCC
4865C–AUTO–01/06
3


3Pages


ATA6026 電子部品, 半導体
3.3 Wake-up and Sleep Mode Strategy
The ATA6026 has 2 modes: Sleep and Active. To change between the two modes, 3 proce-
dures are implemented and described here.
The default state after power-on is Active mode.
1. Go to Sleep
A HIGH to LOW transition at pin EN, followed by a LOW for the time tgotosleep (typically
50 ms), switches the ATA6026 to Sleep mode.
The internal 5V supply VINT, the EN pin input structure, and a certain part of the SCI receiver
are permanently active to ensure proper startup of the system.
2. Go to Active by activating pin EN
The input structure on pin EN consists of a comparator with built-in hysteresis. The input of
the comparator is protected against voltages up to VBATmax.
Pulling the EN pin up to HIGH for a time longer than twakeEN (typically 50 ms) will switch the
ATA6026 to Active mode.
3. Go to Active via the SCI interface
The second possibility for waking up the part is to use the SCI transceiver. In Sleep mode
the SCI receiver is partially active and works in single-ended mode, independent of the sta-
tus of the pin SEM.
The wake-up by SCI requires 2 steps:
a. If the voltage on pin /DATA is below a value of V/DATwake (about VVBAT – 2V), the
receive part of the SCI interface is active (not to be confused with Active mode of
the whole IC). The active receive part is able to detect a valid LOW on the /DATA
pin.
b. If /DATA is LOW for a filter time twakeSCI (typically 50 ms), the IC will change to Active
mode. A short change back to HIGH during the filter time will reset the filter. After
entering the Active mode, this information is stored in a latch.
When the SCI interface is used to switch to Active mode, the EN pin can remain LOW with-
out disturbing the Active mode status.
Figure 3-1 on page 7 illustrates the wake-up by SCI.
6 ATA6026
4865C–AUTO–01/06

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