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FW82815 の電気的特性と機能

FW82815のメーカーはIntelです、この部品の機能は「Graphics and Memory Controller Hub」です。


製品の詳細 ( Datasheet PDF )

部品番号 FW82815
部品説明 Graphics and Memory Controller Hub
メーカ Intel
ロゴ Intel ロゴ 




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FW82815 Datasheet, FW82815 PDF,ピン配置, 機能
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Intel815 Chipset Family: 82815
Graphics and Memory Controller
Hub (GMCH)
Datasheet
June 2000
Document Reference Number: 290688-001

1 Page





FW82815 pdf, ピン配列
82815 GMCH
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Contents
1. Overview.....................................................................................................................................13
1.1. Related Documents .......................................................................................................13
1.2. The Intel815 Chipset Family........................................................................................14
1.3. 82815 GMCH Overview .................................................................................................16
1.4. Host Interface.................................................................................................................17
1.5. System Memory Interface ..............................................................................................17
1.6. Multiplexed AGP and Display Cache Interface ..............................................................18
1.6.1. AGP Interface ..............................................................................................18
1.6.2. Display Cache Interface...............................................................................18
1.7. Hub Interface..................................................................................................................18
1.8. 82815 GMCH Integrated Graphics Support...................................................................19
1.8.1. Display, Digital Video Out, and LCD/Flat Panel/Digital CRT........................19
1.9. System Clocking ............................................................................................................20
1.10. GMCH Power Delivery ...................................................................................................20
2. Signal Description.......................................................................................................................21
2.1.
2.2.
2.3.
2.4.
2.5.
2.6.
2.7.
2.8.
2.9.
2.10.
2.11.
Host Interface Signals ....................................................................................................22
System Memory Interface Signals .................................................................................23
AGP Interface Signals....................................................................................................24
2.3.1.
2.3.2.
2.3.3.
2.3.4.
2.3.5.
AGP Addressing Signals..............................................................................24
AGP Flow Control Signals............................................................................25
AGP Status Signals .....................................................................................25
AGP Clocking Signals (Strobes) ..................................................................26
AGP FRAME# Signals .................................................................................27
Display Cache Interface Signals ....................................................................................29
Hub Interface Signals.....................................................................................................30
Display Interface Signals................................................................................................30
Digital Video Output Signals/TV-Out Pins......................................................................31
Power Signals ................................................................................................................32
Clock Signals .................................................................................................................32
GMCH Power-Up/Reset Strap Options..........................................................................33
Multiplexed Display Cache and AGP Signal Mapping....................................................34
2.11.1. Display Cache Mapping at the AGP Connector ...........................................35
3. Configuration Registers ..............................................................................................................37
3.1. Register Nomenclature and Access Attributes ..............................................................37
3.2. PCI Configuration Space Access ...................................................................................38
3.2.1. PCI Bus Configuration Mechanism ..............................................................38
3.2.2. Logical PCI Bus #0 Configuration Mechanism.............................................39
3.2.3. Primary PCI (PCI0) and Downstream Configuration Mechanism ................39
3.2.4. Internal Graphics Device Configuration Mechanism....................................39
3.2.5. GMCH Register Introduction........................................................................39
3.3. I/O Mapped Registers ....................................................................................................40
3.3.1. CONF_ADDRConfiguration Address Register .........................................40
3.3.2. CONF_DATAConfiguration Data Register ...............................................41
Datasheet
3


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FW82815 電子部品, 半導体
82815 GMCH
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Functional Description.............................................................................................................. 121
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
4.10.
4.11.
System Address Map .................................................................................................. 121
4.1.1. Memory Address Ranges .......................................................................... 122
4.1.2. Compatibility Area ..................................................................................... 123
4.1.3. Extended Memory Area............................................................................. 125
4.1.3.1. System Management Mode (SMM) Memory Range .................... 128
Memory Shadowing ..................................................................................................... 129
I/O Address Space ...................................................................................................... 129
4.3.1. GMCH Decode Rules and Cross-Bridge Address Mapping...................... 129
4.3.2. Address Decode Rules.............................................................................. 130
4.3.2.1. AGP Interface Decode Rules........................................................ 131
4.3.2.2. Legacy VGA Ranges .................................................................... 132
Host Interface .............................................................................................................. 133
4.4.1. Host Bus Device Support .......................................................................... 133
4.4.2. Special Cycles ........................................................................................... 135
System Memory DRAM Interface ................................................................................ 136
4.5.1. DRAM Organization and Configuration ..................................................... 136
4.5.1.1. Configuration Mechanism For DIMMs .......................................... 137
4.5.1.2. DRAM Register Programming ...................................................... 138
4.5.2. DRAM Address Translation and Decoding................................................ 138
4.5.3. DRAM Array Connectivity .......................................................................... 139
4.5.4. SDRAMT Register Programming .............................................................. 140
4.5.5. SDRAM Paging Policy............................................................................... 140
IntelDynamic Video Memory Technology (D.V.M.T.)................................................ 140
Display Cache Interface............................................................................................... 141
4.7.1. Supported DRAM Types for Display Cache Memory ................................ 141
4.7.2. Memory Configurations ............................................................................. 142
4.7.3. Address Translation .................................................................................. 143
4.7.4. Display Cache Interface Timing ................................................................ 143
Internal Graphics Device ............................................................................................. 144
4.8.1. 3D/2D Instruction Processing.................................................................... 144
4.8.2. 3D Engine.................................................................................................. 145
4.8.3. Buffers ....................................................................................................... 145
4.8.4. Setup ......................................................................................................... 146
4.8.5. Texturing.................................................................................................... 146
4.8.6. 2D Operation ............................................................................................. 148
4.8.7. Fixed Blitter (BLT) and Stretch Blitter (STRBLT) Engines......................... 148
4.8.7.1. Fixed BLT Engine ......................................................................... 149
4.8.7.2. Arithmetic Stretch BLT Engine...................................................... 149
4.8.8. Hardware Motion Compensation ............................................................... 149
4.8.9. Hardware Cursor ....................................................................................... 150
4.8.10. Overlay Engine .......................................................................................... 150
4.8.11. Display....................................................................................................... 151
4.8.12. Flat Panel/Digital CRT Interface / 1.8V TV-Out Interface.......................... 152
4.8.13. DDC (Display Data Channel)..................................................................... 153
System Reset for the GMCH ....................................................................................... 154
System Clock Description............................................................................................ 154
Power Management .................................................................................................... 154
4.11.1. Specifications Supported........................................................................... 154
6 Datasheet

6 Page



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部品番号部品説明メーカ
FW82815

Graphics and Memory Controller Hub

Intel
Intel
FW82815

Graphics and Memory Controller Hub

Intel
Intel


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