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COM’L: -4/5/7/B/B-2/A, D/2
20-Pin TTL Programmable Array Logic
s As fast as 4.5 ns maximum propagation delay
s Popular 20-pin architectures: 16L8, 16R8, 16R6,
s Programmable replacement for high-speed TTL
s Register preload for testability
s Power-up reset for initialization
s Extensive third-party software and programmer
support through FusionPLD partners
s 20-Pin DIP and PLCC packages save space
s 28-Pin PLCC-4 package provides ultra-clean
The PAL16R8 Family (PAL16L8, PAL16R8, PAL16R6,
PAL16R4) includes the PAL16R8-5/4 Series which pro-
vides the highest speed in the 20-pin TTL PAL device
family, making the series ideal for high-performance ap-
plications. The PAL16R8 Family is provided with stan-
dard 20-pin DIP and PLCC pinouts and a 28-pin PLCC
pinout. The 28-pin PLCC pinout contains seven extra
ground pins interleaved between the outputs to reduce
noise and increase speed.
The devices provide user-programmable logic for re-
placing conventional SSI/MSI gates and flip-flops at a
reduced chip count.
The family allows the systems engineer to implement
the design on-chip, by opening fuse links to configure
AND and OR gates within the device, according to the
desired logic function. Complex interconnections be-
tween gates, which previously required time-consuming
layout, are lifted from the PC board and placed on sili-
con, where they can be easily modified during proto-
typing or production.
The PAL device implements the familiar Boolean logic
transfer function, the sum of products. The PAL device
is a programmable AND array driving a fixed OR array.
The AND array is programmed to create custom product
terms, while the OR array sums selected terms at the
In addition, the PAL device provides the following
— Variable input/output pin ratio
— Programmable three-state outputs
— Registers with feedback
Product terms with all connections opened assume the
logical HIGH state; product terms connected to both true
and complement of any single input assume the logical
LOW state. Registers consist of D-type flip-flops that are
loaded on the LOW-to-HIGH transition of the clock. Un-
used input pins should be tied to VCC or GND.
The entire PAL device family is supported by the
FusionPLD partners. The PAL family is programmed on
conventional PAL device programmers with appropriate
personality and socket adapter modules. Once the PAL
device is programmed and verified, an additional con-
nection may be opened to prevent pattern readout. This
feature secures proprietary circuits.
PRODUCT SELECTOR GUIDE
Publication# 16492 Rev. D Amendment /0
Issue Date: February 1996
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