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PDF AS8S128K32 Data sheet ( Hoja de datos )
| Número de pieza | AS8S128K32 | |
| Descripción | 128K x 32 SRAM SRAM MEMORY ARRAY | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
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Austin Semiconductor, Inc.
SRAM
AS8S128K32
128K x 32 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-95595: -Q
• SMD 5962-93187: -P or -PN
• MIL-STD-883
FEATURES
• Access times of 15, 17, 20, 25, 35, and 45 ns
• Built in decoupling caps for low noise operation
• Organized as 128K x32; User configured as
256Kx16 or 512K x8
• Operation with single 5 volt supply
• Low power CMOS
• TTL Compatible Inputs and Outputs
• 2V Data Retention, Low power standby
OPTIONS
• Timing
15ns
www.DataSheet4U.com
17ns
20ns
25ns
35ns
45ns
MARKINGS
-15
-17
-20
-25
-35
-45
PIN ASSIGNMENT
(Top View)
68 Lead CQFP (Q & Q1)
66 Lead PGA- Pins 8, 21, 28, 39 are grounds (P)
• Package
Ceramic Quad Flatpack
Q
Ceramic Quad Flatpack
Q1
Pin Grid Array -8 Series
P
Pin Grid Array -8 Series
PN
NOTE: PN indicates a no connect on pins 8, 21, 28, 39
No. 702
No. 802
No. 802
66 Lead PGA- Pins 8, 21, 28, 39 are no connects (PN)
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8S128K32 is a 4 Mega-
bit CMOS SRAM Module organized as 128Kx32-bits and user
configurable to 256Kx16 or 512Kx8. The AS8S128K32 achieves
high speed access, low power consumption and high reliability
by employing advanced CMOS memory technology.
The military temperature grade product is suited for mili-
tary applications.
The AS8S128K32 is offered in a ceramic quad flatpack mod-
ule per SMD-5962-95595 with a maximum height of 0.140 inches.
This module makes use of a low profile, mutlichip module de-
sign.
This device is also offered in a 1.075 inch square ceramic
pin grid array per SMD 5692-93187, which has a maximum height
of 0.195 inches. This package is also a low profile, multi-chip
module design reducing height requirements to a minimum.
For more products and information
please visit our web site at
www.austinsemiconductor.com
CE4
WE4
CE3
WE3
CE2
WE2
CE1
WE1
OE
A0 - 16
M3
M2
M1
M0
I/O 24 - I/O 31
I/O 16 - I/O 23
I/O 8 - I/O 23
I/O 0 - I/O 7
AS8S128K32
Rev. 4.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
SRAM
AS8S128K32
NOTES
1. All voltages referenced to VSS (GND).
2. -3v for pulse width <20ns.
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
open, and f=
1
tRC(MIN)
HZ.
4. This parameter is sampled.
5. Test conditions as specified with output loading as
shown in Fig. 1 unless otherwise noted.
6. tHZCE, tHZOE and tHZWE are specified with CL= 5pF
as in Fig. 2. Transition is measured +/- 200 mV
typical from steady state coltage, allowing for actual
tester RC time constant.
7. At any given temperature and voltage condition,
tHZCE, is less than tLZCE, and tHZWE is less than tLZWE.
8. ?W/E is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and output
enable are held in their active state.
10. Address valid prior to or coincident with latest occurring
chip enable.
11. t = READ cycle time.
RC
12. Chip enable (?C/E) and write enable (?W/E) can initiate and
terminate a WRITE cycle.
13. 32 bit operation
DATA RETENTION ELECTRICAL CHARACTERISTICS
DESCRIPTION
VCC for Retention Data
CONDITIONS
SYMBOL
VDR
MIN
2
MAX
--
Data Retention Current
CE\ > VCC - 0.2V VCC = 2.0V ICCDR
--
6
VIN > VCC - 0.2V
VCC = 3V
ICCDR
--
11.6
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR
tR
0
tRC
--
UNITS
V
mA
mA
NOTES
ns 4
ns 4, 11
Vcc
VIH
CE\
VIL
LOW VCC DATA RETENTION WAVEFORM
tCDR
DATA RETENTION MODE
VDR >2V
4.5V 4.5V
VDR
tR
AS8S128K32
Rev. 4.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
SRAM
AS8S128K32
ORDERING INFORMATION
EXAMPLE: AS8S128K32Q-25/XT
Device Number
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
Package
Type
Q
Q
Q
Q
Q
Q
Speed
ns
-15
-17
-20
-25
-35
-45
Process
/*
/*
/*
/*
/*
/*
EXAMPLE: AS8S128K32PN-20/883C
Device Number
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
Package
Type
P
PN
P
PN
P
PN
P
PN
P
PN
P
PN
Speed
ns
-15
-15
-17
-17
-20
-20
-25
-25
-35
-35
-45
-45
Process
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
EXAMPLE: AS8S128K32Q1-15/IT
Device Number
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
Package
Type
Q1
Q1
Q1
Q1
Q1
Q1
Speed
ns
-15
-17
-20
-25
-35
-45
Process
/*
/*
/*
/*
/*
/*
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
883C = Full Military Processing
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PACKAGE NOTES
P = Pins 8, 21, 28, and 39 are grounds.
PN = Pins 8, 21, 28, and 39 are no connects.
AS8S128K32
Rev. 4.0 5/03
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AS8S128K32.PDF ] | |
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