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PDF ISL8103 Data sheet ( Hoja de datos )
| Número de pieza | ISL8103 | |
| Descripción | Three-Phase Buck PWM Controller | |
| Fabricantes | Intersil Corporation | |
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ISL8103
®
Data Sheet
February 15, 2006
FN9246.0
Three-Phase Buck PWM Controller with
High Current Integrated MOSFET Drivers
The ISL8103 is a three-phase PWM control IC with
integrated MOSFET drivers. It provides a precision voltage
regulation system for multiple applications including, but not
limited to, high current low voltage point-of-load converters,
embedded applications and other general purpose low
voltage medium to high current applications.The integration
of power MOSFET drivers into the controller IC marks a
departure from the separate PWM controller and driver
configuration of previous multi-phase product families. By
reducing the number of external parts, this integration allows
for a cost and space saving power management solution.
Output voltage can be programmed using the on-chip DAC
or an external precision reference. A two bit code programs
the DAC reference to one of 4 possible values (0.6V, 0.9V,
1.2V and 1.5V). A unity gain, differential amplifier is provided
for remote voltage sensing, compensating for any potential
difference between remote and local grounds. The output
voltage can also be offset through the use of single external
resistor. An optional droop function is also implemented and
can be disabled for applications having less stringent output
voltage variation requirements or experiencing less severe
step loads.
A unique feature of the ISL8103 is the combined use of both
DCR and rDS(ON) current sensing. Load line voltage
positioning and overcurrent protection are accomplished
through continuous inductor DCR current sensing, while
rDS(ON) current sensing is used for accurate channel-current
balance. Using both methods of current sampling utilizes the
best advantages of each technique.
Protection features of this controller IC include a set of
sophisticated overvoltage and overcurrent protection.
Overvoltage results in the converter turning the lower
MOSFETs ON to clamp the rising output voltage and protect
the load. An OVP output is also provided to drive an optional
crowbar device. The overcurrent protection level is set
through a single external resistor. Other protection features
include protection against an open circuit on the remote
sensing inputs. Combined, these features provide advanced
protection for the output load.
Features
• Integrated Multi-Phase Power Conversion
- 1, 2, or 3 Phase Operation
• Precision Output Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.8% System Accuracy Over Temperature
(for REF=0.6V and 0.9V)
- ±0.5% System Accuracy Over Temperature
(for REF=1.2V and 1.5V)
- Usable for Output Voltages not Exceeding 2.3V
- Adjustable Reference-Voltage Offset
• Precision Channel Current Sharing
- Uses Loss-Less rDS(ON) Current Sampling
• Optional Load Line (Droop) Programming
- Uses Loss-Less Inductor DCR Current Sampling
• Variable Gate-Drive Bias - 5V to 12V
• Internal or External Reference Voltage Setting
- On-Chip Adjustable Fixed DAC Reference voltage with
2-bit Logic Input Selects from Four Fixed Reference
Voltages (0.6V, 0.9V, 1.2V, 1.5V)
- Reference can be Changed Dynamically
- Can use an External Voltage Reference
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
- OVP Pin to Drive Optional Crowbar Device
• Selectable Operation Frequency up to 1.5MHz per Phase
• Digital Soft-Start
• Capable of Start-up in a Pre-Biased Load
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• High Current DDR/Chipset Core Voltage Regulators
• High Current, Low Voltage DC/DC Converters
• High Current, Low Voltage FPGA/ASIC DC/DC
Converters
Ordering Information
PART NUMBER*
PART MARKING
TEMERATURE (°C)
PACKAGE
PKG. DWG. #
ISL8103CRZ (Note)
ISL8103CRZ
0 to 70
40 Ld 6x6 QFN (Pb-free)
L40.6x6
ISL8103IRZ (Note)
ISL8103IRZ
-40 to 85
40 Ld 6x6 QFN (Pb-free)
L40.6x6
ISL8103EVAL1
Evaluation Platform
* Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL8103
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Supply Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
Absolute Boot Voltage, VBOOT . . . . . . . . GND - 0.3V to GND + 36V
Phase Voltage, VPHASE . . . . . . . . GND - 0.3V to 15V (PVCC = 12)
GND - 8V (<400ns, 20µJ) to 24V (<200ns, VBOOT-PHASE = 12V)
Upper Gate Voltage, VUGATE . . . . VPHASE - 0.3V to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
Lower Gate Voltage, VLGATE. . . . . . . . GND - 0.3V to PVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Information
Thermal Resistance
θJA (°C/W) θJC (°C/W)
QFN Package (Notes 1, 2) . . . . . . . . . .
32
3.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Recommended Operating Conditions
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5%
Ambient Temperature (ISL8103CRZ) . . . . . . . . . . . . . . 0°C to 70°C
Ambient Temperature (ISL8103IRZ) . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
BIAS SUPPLY AND INTERNAL OSCILLATOR
Input Bias Supply Current
Gate Drive Bias Current
VCC POR (Power-On Reset) Threshold
IVCC; ENLL = high
IPVCC; ENLL = high; all gate outputs open,
Fsw = 250kHz
VCC Rising
VCC Falling
PVCC POR (Power-On Reset) Threshold
PVCC Rising
PVCC Falling
Oscillator Ramp Amplitude (Note 3)
Maximum Duty Cycle (Note 3)
VPP
CONTROL THRESHOLDS
ENLL Rising Threshold
ENLL Hysteresis
COMP Shutdown Threshold
COMP Falling
REFERENCE AND DAC
System Accuracy (DAC = 0.6V, 0.9V)
DROOP connected to IREF
System Accuracy (DAC = 1.2V, 1.50V)
DROOP connected to IREF
DAC Input Low Voltage (REF0, REF1)
DAC Input High Voltage (REF0, REF1)
External Reference (Note 3)
OFS Sink Current Accuracy (Negative Offset)
OFS Source Current Accuracy (Positive Offset)
ROFS = 30kΩ from OFS to VCC
ROFS = 10kΩ from OFS to GND
MIN TYP MAX UNITS
- 15 20 mA
- 0.8 2.00 mA
4.25 4.38 4.50 V
3.75 3.88 4.00 V
4.25 4.38 4.50 V
3.75 3.88 4.00 V
- 1.50 - V
- 66.6 - %
- 0.66 - V
- 100 - mV
0.1 0.25 0.4 V
-0.8 -
0.8 %
-0.5 -
0.5 %
- - 0.4 V
0.8 -
-V
0.6 1.75 V
47.5 50.0 52.5 µA
47.5 50.0 52.5 µA
5 FN9246.0
February 15, 2006
5 Page 
ISL8103
VCOMP
+
-
FILTER f(s)
PWM1
+
-
SAWTOOTH SIGNAL
IER
IAVG
-
÷N
+
Σ
TO GATE
CONTROL
LOGIC
I3
I2
I1
NOTE: Channel 2 and 3 are optional.
FIGURE 3. CHANNEL 1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
Current Sampling
In order to realize proper current balance, the currents in
each channel must be sampled every switching cycle. This
sampling occurs during the forced off-time, following a PWM
transition low. During this time the current sense amplifier
uses the ISEN inputs to reproduce a signal proportional to
the inductor current, IL. This sensed current, ISEN, is simply
a scaled version of the inductor current. The sample window
opens exactly 1/6 of the switching period, tSW, after the
PWM transitions low. The sample window then stays open
the rest of the switching cycle until PWM transitions high
again, as illustrated in Figure 4.
The sampled current, at the end of the tSAMPLE, is
proportional to the inductor current and is held until the next
switching period sample. The sampled current is used only
for channel current balance.
IL
PWM
SWITCHING PERIOD
ISEN
SAMPLING PERIOD
OLD SAMPLE
CURRENT
NEW SAMPLE
CURRENT
TIME
FIGURE 4. SAMPLE AND HOLD TIMING
The ISL8103 supports MOSFET rDS(ON) current sensing to
sample each channel’s current for channel current balance.
The internal circuitry, shown in Figure 5 represents channel
n of an N-channel converter. This circuitry is repeated for
each channel in the converter, but may not be active
depending on the status of the PVCC3 and PVCC2 pins, as
described in the PWM Operation section.
In ISEN = IL x-r--D-R----SI--S--(---OE----N-N-----)
SAMPLE
&
HOLD
-
+
ISL8103 INTERNAL CIRCUIT
VIN
CHANNEL N
UPPER MOSFET
IL
ISEN(n)
RISEN
-
ILx rDS(ON)
CHANNEL N
+
LOWER MOSFET
EXTERNAL CIRCUIT
FIGURE 5. ISL8103 INTERNAL AND EXTERNAL CURRENT-
SENSING CIRCUITRY FOR CURRENT BALANCE
The ISL8103 senses the channel load current by sampling
the voltage across the lower MOSFET rDS(ON), as shown in
Figure 5. A ground-referenced operational amplifier, internal
to the ISL8103, is connected to the PHASE node through a
resistor, RISEN. The voltage across RISEN is equivalent to
the voltage drop across the rDS(ON) of the lower MOSFET
while it is conducting. The resulting current into the ISEN pin
is proportional to the channel current, IL. The ISEN current is
sampled and held as described in the Current Sampling
section. From Figure 5, the following equation for In is
derived where IL is the channel current.
In = IL ⋅ r---DR----S-I-S--(--OE----N-N----)
(EQ. 3)
Output Voltage Setting
The ISL8103 uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
the REF1, REF0 pins. The DAC decodes the 2-bit logic
signals into one of the discrete voltages shown in Table 1.
Each REF0 and REF1 pins are pulled up to an internal 1.2V
voltage by weak current sources (40µA current, decreasing
to 0 as the voltage at the REF0, REF1 pins varies from 0 to
the internal 1.2V pull-up voltage). External pull-up resistors
or active-high output stages can augment the pull-up current
sources, up to a voltage of 5V. The DAC pin must be
connected to REF pin through a 1-5kΩ resistor and a filter
capacitor (0.022µF) is connected between REF and GND.
The ISL8103 accommodates the use of external voltage
reference connected to REF pin if a different output voltage
is required. The DAC voltage must be set at least as high as
the external reference. The error amp internal noninverting
input is the lower of REF or (DAC +300mV).
A third method for setting the output voltage is to use a
resistor divider (RP1, RS1) from the output terminal (VOUT)
11 FN9246.0
February 15, 2006
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet ISL8103.PDF ] | |
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