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PDF ISL6884 Data sheet ( Hoja de datos )
| Número de pieza | ISL6884 | |
| Descripción | CCFL Brightness Controller | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
March 9, 2006
ISL6884
FN9265.0
CCFL Brightness Controller
ISL6884 controls Pulse Width Modulated Dimming for up to
8 inverters to supply power to up to 40 Cold Cathode
Fluorescent Lamps (CCFL) for back lighting in large LCD
displays.
The ISL6884 brightness controller provides an I2C interface
for dimming control, enable, status, and brightness balance.
The duty cycle of all 8 DPWM outputs is adjusted with a
Master Brightness Control register. The duty cycle of each of
the 8 DPWM outputs can be offset from the master
brightness to adjust for uniform brightness.
The PWM dimming frequency can be set by an internal,
adjustable oscillator or synchronized to an external source to
minimize interference with video.
ISL6884’s slave address is:
• 1101_1111 for reading
• 1101_1110 for writing
Ordering Information
PART
NUMBER
TEMP. RANGE
(oC)
PACKAGE
PKG.
DWG. #
ISL6884IAZ
(See Note)
-40 to 85
20 Ld SSOP
(Pb-free)
M20.15
ISL6884IAZ-T
(See Note)
-40 to 85
20 Ld SSOP Tape M20.15
and Reel
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Wide Supply Voltage Range of 3.0V to 5.5V
• Dimming
- I2C dimming control input
- PWM dimming can be synchronized to an external
source or set by an internal, adjustable oscillator.
- 8 channel dimming allows the user to balance the
brightness of the CCFL lamps via I2C control
- User programmable fault time out
• User Programmable Fault Time Out
• I2C Status Output
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL6884
(20 LD SSOP)
TOP VIEW
LAMP_ON 1
TESTEN 2
GNDPLL 3
PLL1 4
EN 5
DPWM_SYNC 6
OSCTEST 7
SCL 8
SDA 9
GND 10
20 VDD
19 REGCAP
18 DPWM_8
17 DPWM_7
16 DPWM_6
15 DPWM_5
14 DPWM_4
13 DPWM_3
12 DPWM_2
11 DPWM_1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6884
Absolute Maximum Ratings
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Input/Output Voltage . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
Thermal Information
Thermal Resistance (Typical, Notes 1)
20 Ld SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
θJA (°C/W)
110
Thermal Information
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SSOP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
POWER ON RESET
VDD Rising
VDD Falling
POR Hysteresis
VOLTAGE REGULATOR
PORrising
PORfalling
PORhyst
2.4 2.7 3.0 V
2.2 2.5 2.7 V
- 200 - mV
Regulated Voltage
Vreg
External Capacitor = 1µF, ESR<1Ω
LOGIC LEVEL INPUTS (EN, DPWM_SYNC, LAMPON)
2.3 2.5 2.7 V
V In High
V In Low
Hysteresis
VIHLOGIC
VILLOGIC
Vhyst
2.6 -
-V
- - 0.8 V
- 140 - mV
Input Current
I2C
I_IN Vin = VDD
Vin = 0V
- 10 - nA
- -10 - nA
V In Low
V In High
Schmitt Trigger Input Hysteresis
V Out Low
SDA, SCL Rise Time
VIL
VIH
Vhys
VOL
Trise_I2C
I in low = 3mA
Cload = 200pF
Rpullup = 1700, 30%-70%
- - 0.3*VDD
0.7*VDD
-
-
- 0.05*VDD -
- - 0.4
- 300 -
V
V
V
V
ns
SDA, SCL Fall Time
Tfall_I2C
Cload = 200pF
Rpullup = 1700, 30%-70%
- - 300 ns
5 FN9265.0
March 9, 2006
5 Page 
ISL6884
I2C Bus General Description
Introduction
(Refer to Philips I2C Specification, Rev. 2.1)
The I2C bus is a 2 wire communication bus for integrated
circuits. I2C, I2C or IIC are commonly used instead of the
formal name Inter-Integrated-Circuit bus. The 2 wires are the
SCL (Serial CLock) and SDA (Serial DAta). All ICs on the
bus are connected to the SCL and SDA lines. SCL and SDA
pins on each device are bidirectional and can act as either
inputs or open drain outputs. Which device is transmitting
and receiving is determined by the bus protocol which will be
described below.
VDD
CPU
I2C Master
SCL
control
input
output
SDA input
control output
I2C Slave
input
output
SCL
control
input SDA
output control
state
machine,
registers,
memory,
etc.
I2C Slave
input
output
SCL
control
input SDA
output control
state
machine,
registers,
memory,
etc.
to other
slave devices
A typical I2C bus system is made of a ‘master’ that initiates
communication (usually a microprocessor) and one or more
‘slaves’ that respond to commands from the master. Each
slave has a device address. In a typical communication
sequence, the master will initiate communication with a ‘start
condition’ followed by the address of one of the slave
devices. The slave device must acknowledge that it
recognizes its address. After receiving the acknowledge, the
master will transmit one or more bytes of commands and
data. If the slave device is an EEPROM the command is the
address within the EEPROM that is to be read or written. If
data is to be written to the EEPROM the master transmits it
after the command.
START and STOP Conditions
As shown in Figure 1, START condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW. Refer to Figure 2.
SDA
SCL
DATA LINE CHANGE
STABLE OF DATA
DATA VALID ALLOWED
FIGURE 2. DATA VALIDITY
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 3).
The peripheral that acknowledges has to pull down (LOW)
the SDA line during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
SCL
SDA
START
12 89
MSB
ACKNOWLEDGE
FROM SLAVE
FIGURE 3. ACKNOWLEDGE ON THE I2C BUS
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
FIGURE 1. START AND STOP WAVEFORMS
11 FN9265.0
March 9, 2006
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ISL6884.PDF ] | |
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