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PDF ISL6614B Data sheet ( Hoja de datos )
| Número de pieza | ISL6614B | |
| Descripción | Dual Advanced Synchronous Rectified Buck MOSFET Drivers | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
Dual Advanced Synchronous Rectified
Buck MOSFET Drivers with Pre-POR OVP
The ISL6614B integrates two ISL6613B MOSFET drivers
and is specifically designed to drive two Channel MOSFETs
in a synchronous rectified buck converter topology. This
driver combined with HIP63xx or ISL65xx Multi-Phase Buck
PWM controllers and N-Channel MOSFETs forms complete
core-voltage regulator solutions for advanced
microprocessors.
The ISL6614B features 7V rising threshold and drives both
the upper and lower gates simultaneously over a range from
5V to 12V. This drive-voltage provides the flexibility
necessary to optimize applications involving trade-offs
between gate charge and conduction losses. This driver is
optimized for POL DC/DC Converters for IBA Systems.
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. These products add an overvoltage protection feature
operational before VCC exceeds its turn-on threshold, at
which the PHASE node is connected to the gate of the low
side MOSFET (LGATE). The output voltage of the converter
is then limited by the threshold of the low side MOSFET,
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during start-up.
The ISL6614B also features a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.
ISL6614B
January 3, 2006
FN9206.2
Features
• Pin-to-pin Compatible with HIP6602 SOIC family
• Quad N-Channel MOSFET Drives for Two Synchronous
Rectified Bridges
• Low VCC Rising Threshold (7V) for IBA Applications
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- Auto-zero of rDS(ON) Conduction Offset Effect
• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
• Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 1MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Optimized for POL DC/DC Converters for IBA Systems
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief 400 and 417 for Power Train Design,
Layout Guidelines, and Feedback Compensation Design
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6614B
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to VPVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to VPVCC + 0.3V
PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 15VDC
GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND<36V)
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Information
Thermal Resistance (Typical Notes 1, 2, 3) θJA(°C/W) θJC(°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
90
N/A
QFN Package (Notes 2, 3). . . . . . . . . .
46
9
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V to 13.2V
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V ±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
4. Guaranteed by design. Not 100% tested in production.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Bias Supply Current
Gate Drive Bias Current
POWER-ON RESET AND ENABLE
IVCC
IPVCC
fPWM = 300kHz, VPVCC = 12V
fPWM = 300kHz, VPVCC = 12V
- 7.1 - mA
- 9.7 - mA
VCC Rising Threshold
0°C to 85°C
6.60 6.9 7.25
V
VCC Rising Threshold
-40°C to 85°C
5.60 7.25 V
VCC Falling Threshold
0°C to 85°C
5.20 5.4 5.90
V
VCC Falling Threshold
-40°C to 85°C
4.20 5.90 V
PWM INPUT (See Timing Diagram on Page 7)
Input Current
PWM Rising Threshold
IPWM
VPWM = 5V
VPWM = 0V
VCC = 12V
- 500 -
- -460 -
- 3.00 -
µA
µA
V
PWM Falling Threshold
VCC = 12V
- 2.00 -
V
Typical Three-State Shutdown Window
VCC = 12V
1.80 2.40 V
Three-State Lower Gate Falling Threshold
VCC = 12V
- 1.50 -
V
Three-State Lower Gate Rising Threshold
VCC = 12V
- 1.00 -
V
Three-State Upper Gate Rising Threshold
VCC = 12V
- 3.20 -
V
Three-State Upper Gate Falling Threshold
VCC = 12V
- 2.60 -
V
Shutdown Holdoff Time
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-On Propagation Delay (Note 4)
tTSSHD
- 245 -
tRU VPVCC = 12V, 3nF Load, 10% to 90%
-
26
-
tRL VPVCC = 12V, 3nF Load, 10% to 90% - 18 -
tFU VPVCC = 12V, 3nF Load, 90% to 10%
-
18
-
tFL VPVCC = 12V, 3nF Load, 90% to 10% - 12 -
tPDHU
VPVCC = 12V, 3nF Load, Adaptive
- 10 -
ns
ns
ns
ns
ns
ns
5 FN9206.2
January 3, 2006
5 Page 
ISL6614B
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
E
-B-
H
0.25(0.010) M B M
123
-A-
D
SEATING PLANE
A
L
h x 45o
-C-
e A1
B
0.25(0.010) M C A M B S
α
0.10(0.004)
C
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.0532 0.0688 1.35
1.75
-
A1 0.0040 0.0098 0.10 0.25
-
B 0.013 0.020 0.33 0.51
9
C
0.0075 0.0098 0.19
0.25
-
D
0.3367 0.3444 8.55
8.75
3
E
0.1497 0.1574 3.80
4.00
4
e 0.050 BSC 1.27 BSC -
H
0.2284 0.2440 5.80
6.20
-
h
0.0099 0.0196 0.25
0.50
5
L 0.016 0.050 0.40 1.27
6
N 14
14 7
α 0o 8o 0o 8o -
Rev. 0 12/93
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11 FN9206.2
January 3, 2006
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ISL6614B.PDF ] | |
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