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PDF ISL6445 Data sheet ( Hoja de datos )
| Número de pieza | ISL6445 | |
| Descripción | Step-Down PWM Controller | |
| Fabricantes | Intersil Corporation | |
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®
PRELIMINARY
Data Sheet
September 9, 2005
ISL6445
FN9230.0
1.4MHz Dual, 180° Out-of-Phase,
Step-Down PWM Controller
The ISL6445 is a high-performance, dual-output PWM
controller optimized for converting wall adapter, battery or
network intermediate bus DC input supplies into the system
supply voltages required for a wide variety of applications.
Each output is adjustable down to 0.8V. The two PWMs are
synchronized 180o out of phase reducing the RMS input
current and ripple voltage.
The ISL6445 incorporates several protection features. An
adjustable overcurrent protection circuit monitors the output
current by sensing the voltage drop across the lower
MOSFET. Hiccup mode overcurrent operation protects the
DC/DC components from damage during output
overload/short circuit conditions. Each PWM has an
independent logic-level shutdown input (SD1 and SD2).
A single PGOOD signal is issued when soft-start is complete
on both PWM controllers and their outputs are within 10% of
the set point. Thermal shutdown circuitry turns off the device
if the junction temperature exceeds +150°C.
Pinout
ISL6445 (QSOP)
TOP VIEW
1 LGATE2 LGATE1 24
2 BOOT2 BOOT1 23
3 UGATE2 UGATE1 22
4 PHASE2 PHASE1 21
5 ISEN2
ISEN1 20
6 PGOOD PGND 19
7 VCC5
SD1 18
8 SD2
SS1 17
9 SS2
SGND 16
10 OCSET2 OCSET1 15
11 FB2
FB1 14
12 VIN
BIAS 13
Features
• Wide Input Supply Voltage Range
- 5.6V to 24V
- 4.5V to 5.6V
• Two Independently Programmable Output Voltages
• Switching Frequency . . . . . . . . . . . . . . . . . . . . . . .1.4MHz
• Out of Phase PWM Controller Operation
- Reduces Required Input Capacitance and Power
Supply Induced Loads
• No External Current Sense Resistor
- Uses Lower MOSFET’s rDS(ON)
• Programmable Soft-Start
• Extensive Circuit Protection Functions
- PGOOD
- UVLO
- Overcurrent
- Overtemperature
- Independent Shutdown for Both PWMs
• Excellent Dynamic Response
- Voltage Feed-Forward with Current Mode Control
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Power Supplies with Two Outputs
• xDSL Modems/Routers
• DSP, ASIC, and FPGA Power Supplies
• Set-Top Boxes
• Dual Output Supplies for DSP, Memory, Logic, µP Core
and I/O
• Telecom Systems
Ordering Information
PART
PART
TEMP.
PKG.
NUMBER MARKING RANGE (°C) PACKAGE DWG. #
ISL6445IAZ* ISL6445IAZ -40 to 85 24 Ld QSOP M24.15
(See Note)
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
*Add “-TK” suffix for tape and reel.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6445
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
Schematic. VIN = 5.6V to 24V, or VCC5 = 5V ±10%, TA = -40°C to 85°C (Note 3),
Typical values are at TA = 25°C (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER ERROR AMPLIFIERS
DC Gain (Note 7)
80 88 - dB
Gain-Bandwidth Product (Note 7)
5.9 -
- MHz
Slew Rate (Note 7)
- 2.0 - V/µs
Maximum Output Voltage (Note 7)
0.9 - - V
Minimum Output Voltage (Note 7)
- - 3.6 V
PWM CONTROLLER GATE DRIVERS (Note 8)
Sink/Source Current
- 400 - mA
Upper Drive Pull-Up Resistance
VCC5 = 4.5V
-8-
Upper Drive Pull-Down Resistance
VCC5 = 4.5V
- 3.2 -
Lower Drive Pull-Up Resistance
VCC5 = 4.5V
-8-
Lower Drive Pull-Down Resistance
VCC5 = 4.5V
- 1.8 -
Rise Time
Fall Time
POWER GOOD AND CONTROL FUNCTIONS
COUT = 1000pF
COUT = 1000pF
- 18 - ns
- 18 - ns
PGOOD LOW Level Voltage
Pull-up = 100kΩ
-
0.1 0.5
V
PGOOD Leakage Current
- - ±1.0 µA
PGOOD Upper Threshold, PWM 1 and 2
Fraction of set point
105 - 120 %
PGOOD Lower Threshold, PWM 1 and 2
Fraction of set point
80 - 95 %
ISEN and CURRENT LIMIT
Full Scale Input Current (Note 9)
- 32 - µA
Overcurrent Threshold (Note 9)
ROCSET = 110kΩ
- 64 - µA
OCSET (Current Limit) Voltage
- 1.75 -
V
SOFT-START
Soft-Start Current
- 5 - µA
PROTECTION
Thermal Shutdown
Rising
- 150 -
°C
Hysteresis
- 20 - °C
NOTES:
2. Specifications at -40°C and 85°C are guaranteed by design, not production tested.
3. In normal operation, where the device is supplied with voltage on the VIN pin, the VCC_5V pin provides a 5V output capable of 60mA (min).
When the VCC_5V pin is used as a 5V supply input, the internal LDO regulator is disabled and the VIN input pin must be connected to the
VCC_5V pin. (Refer to the Pin Descriptions section for more details.)
4. This is the total shutdown current with VIN = VCC_5V = PVCC = 5V.
5. Operating current is the supply current consumed when the device is active but not switching. It does not include gate drive current.
6. The peak-to-peak sawtooth amplitude is production tested at 12V only; at 5V this parameter is guaranteed by design.
7. Guaranteed by design; not production tested.
8. Not production tested; guaranteed by characterization only.
9. Guaranteed by design. The full scale current of 32µA is recommended for optimum current sample and hold operation. See the Feedback Loop
Compensation Section below.
5 FN9230.0
September 9, 2005
5 Page 
ISL6445
Over-Temperature Protection
The IC incorporates an over-temperature protection circuit
that shuts the IC down when a die temperature of 150°C is
reached. Normal operation resumes when the die
temperatures drops below 130°C through the initiation of a
full soft-start cycle.
Feedback Loop Compensation
To reduce the number of external components and to
simplify the process of determining compensation
components, both PWM controllers have internally
compensated error amplifiers. To make internal
compensation possible several design measures were
taken.
First, the ramp signal applied to the PWM comparator is
proportional to the input voltage provided via the VIN pin.
This keeps the modulator gain constant with variation in the
input voltage. Second, the load current proportional signal is
derived from the voltage drop across the lower MOSFET
during the PWM time interval and is subtracted from the
amplified error signal on the comparator input. This creates
an internal current control loop. The resistor connected to
the ISEN pin sets the gain in the current feedback loop. The
following expression estimates the required value of the
current sense resistor depending on the maximum operating
load current and the value of the MOSFET’s rDS(ON).
RCS ≥ -(--I--M-----A----X--3-)--2-(--R-µ----AD----S----o---n----)---)
Choosing RCS to provide 32µA of current to the current
sample and hold circuitry is recommended but values down
to 2µA and up to 100µA can be used.
Due to the current loop feedback, the modulator has a single
pole response with -20dB slope at a frequency determined
by the load.
FPO = 2----π-----⋅---R----1-O-----⋅---C-----O-- ,
where RO is load resistance and CO is load capacitance. For
this type of modulator, a Type 2 compensation circuit is
usually sufficient.
Figure 16 shows a Type 2 amplifier and its response along
with the responses of the current mode modulator and the
converter. The Type 2 amplifier, in addition to the pole at
origin, has a zero-pole pair that causes a flat gain region at
frequencies in between the zero and the pole.
FZ = 2----π-----⋅---R--1---2----⋅---C-----1- = 6kHz
FP = 2----π-----⋅---R--1---1----⋅---C-----2- = 600kHz
CONVERTER
EA
GM = 17.5dB
MODULATOR
FPO
C2
R2 C1
R1
TYPE 2 EA
GEA = 18dB
FZ FP
FC
FIGURE 16. FEEDBACK LOOP COMPENSATION
The zero frequency, the amplifier high-frequency gain, and
the modulator gain are chosen to satisfy most typical
applications. The crossover frequency will appear at the
point where the modulator attenuation equals the amplifier
high frequency gain. The only task that the system designer
has to complete is to specify the output filter capacitors to
position the load main pole somewhere within one decade
lower than the amplifier zero frequency. With this type of
compensation plenty of phase margin is easily achieved due
to zero-pole pair phase ‘boost’.
Conditional stability may occur only when the main load pole
is positioned too much to the left side on the frequency axis
due to excessive output filter capacitance. In this case, the
ESR zero placed within the 1.2kHz to 30kHz range gives
some additional phase ‘boost’. Some phase boost can also
be achieved by connecting capacitor CZ in parallel with the
upper resistor R1 of the divider that sets the output voltage
value. Please refer to the output inductor and capacitor
selection sections for further details.
Layout Guidelines
Careful attention to layout requirements is necessary for
successful implementation of a ISL6445 based DC/DC
converter. The ISL6445 switches at a very high frequency
and therefore the switching times are very short. At these
switching frequencies, even the shortest trace has
significant impedance. Also the peak gate drive current rises
significantly in extremely short time. Transition speed of the
current from one device to another causes voltage spikes
across the interconnecting impedances and parasitic circuit
elements. These voltage spikes can degrade efficiency,
generate EMI, increase device overvoltage stress and
ringing. Careful component selection and proper PC board
layout minimizes the magnitude of these voltage spikes.
11 FN9230.0
September 9, 2005
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ISL6445.PDF ] | |
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