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ISL6440A の電気的特性と機能

ISL6440AのメーカーはIntersil Corporationです、この部品の機能は「Advanced PWM and Triple Linear Power Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6440A
部品説明 Advanced PWM and Triple Linear Power Controller
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL6440A Datasheet, ISL6440A PDF,ピン配置, 機能
TM
Data Sheet
October 2001
ISL6440A
File Number 9041
Advanced PWM and Triple Linear Power
Controller for Gateway Applications
The ISL6440A provides the power control and protection for
four output voltages required by microprocessors used in
high-performance, graphics-intensive gateway applications.
The IC integrates a voltage-mode PWM controller and three
linear controllers, as well as the monitoring and protection
functions into a 28 lead SOIC package.
The synchronous rectified buck converter includes an Intel®-
compatible, TTL five-input, digital-to-analog converter (DAC)
that adjusts the core PWM output voltage from 1.3VDC to
2.05VDC in 0.05V steps and from 2.1VDC to 3.5VDC in 0.1V
increments. The precision reference and voltage-mode
control provide ±1% static regulation. A TTL-compatible
signal applied to the SELECT pin dictates which method of
control is used for the AGP bus power. A low state results in
linear control of the AGP bus to 1.5V, while a high state
transitions the output through a linearly controlled soft-start
to 3.3V, followed by full enhancement of the external
MOSFET to pass the input voltage. The other two linear
regulators provide fixed output voltages of 1.5V GTL bus
power and 1.8V power for the north/south bridge core and/or
cache memory. These levels are user-adjustable by means
of an external resistor divider and pulling the FIX pin low. All
linear controllers can employ either N-Channel MOSFETs or
bipolar NPNs for the pass transistor.
The ISL6440A monitors all the output voltages. A single
power good signal is issued when the core is within ±10% of
the DAC setting and all other outputs are above their under-
voltage levels. Additional built-in overvoltage protection for
the core output uses the lower MOSFET to prevent output
voltages above 115% of the DAC setting. The PWM
controller’s overcurrent function monitors the output current
by using the voltage drop across the upper MOSFET’s
rDS(ON).
Ordering Information
PART NUMBER
ISL6440ACB
TEMP.
RANGE (oC)
PACKAGE
0 to 70 28 Ld SOIC
PKG.
NO.
M28.3
Features
• Provides four regulated voltages
- Microprocessor core, AGP bus, memory, and GTL bus
power
• Drives N-Channel MOSFETs
• Linear regulator drives compatible with both MOSFET and
bipolar series pass transistors
• Fixed or externally resistor-adjustable linear outputs
• Simple single-loop control design
- Voltage-mode PWM control
• Fast PWM converter transient response
- High-bandwidth error amplifier
- Full 0–100% duty ratio
• Excellent output voltage regulation
- Core PWM output: ±1% over temperature
- Other outputs: ±3% over temperature
• TTL-compatible 5-bit DAC core output voltage selection
- Shutdown feature removed when all inputs high
- Wide range 1.3VDC to 3.5VDC
• Power-good output voltage monitor
• Overvoltage and overcurrent fault monitors
- Switching regulator does not require extra current
Sensing element, uses upper MOSFET’s rDS(ON)
• Small converter size
- Constant frequency operation
- 200kHz free-running oscillator; programmable from
50kHz to over 1MHz
- Small external component count
Applications
• Power regulation for gateway processors
Pinout
ISL6440A (SOIC)
TOP VIEW
DRIVE2 1
FIX 2
VID4 3
VID3 4
VID2 5
VID1 6
VID0 7
PGOOD 8
SD 9
VSEN2 10
SELECT 11
SS 12
FAULT/RT 13
VSEN4 14
28 VCC
27 UGATE
26 PHASE
25 LGATE
24 PGND
23 OCSET
22 VSEN1
21 FB
20 COMP
19 VSEN3
18 DRIVE3
17 GND
16 VAUX
15 DRIVE4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001. All Rights Reserved
Intel® is a registered trademark of Intel Corporation.

1 Page





ISL6440A pdf, ピン配列
Simplified Power System Diagram
+5VIN
+3.3VIN
VOUT2
Q3
VOUT3
Q4
ISL6440A
LINEAR
CONTROLLER
PWM
CONTROLLER
ISL6440A
LINEAR
CONTROLLER
LINEAR
CONTROLLER
Q1
VOUT1
Q2
Q5 VOUT4
Typical Application
+12VIN
+5VIN
LIN
CIN
VCC
+3.3VIN
VOUT2
1.5V OR 3.3VIN
TYPEDET
VOUT3
1.5V
COUT3
VOUT4
1.8V
COUT4
Q3
COUT2
Q4
DRIVE2
VSEN2
SELECT
VAUX
DRIVE3
VSEN3
ISL6440A
FIX
Q5 DRIVE4
VSEN4
CSS
SS
GND
OCSET
PGOOD
UGATE
PHASE
LGATE
PGND
VSEN1
FB
COMP
POWERGOOD
Q1
LOUT1
VOUT1
1.3V TO 3.5V
Q2 COUT1
FAULT / RT
VID0
VID1
VID2
VID3
VID4
3


3Pages


ISL6440A 電子部品, 半導体
ISL6440A
Functional Pin Descriptions
VCC (Pin 28)
Provide a 12V bias supply for the IC to this pin. This pin also
provides the gate bias charge for all the MOSFETs
controlled by the IC. The voltage at this pin is monitored for
power-on reset (POR) purposes.
GND (Pin 17)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
PGND (Pin 24)
This is the power ground connection. Tie the synchronous
PWM converter’s lower MOSFET source to this pin.
VAUX (Pin 16)
This pin provides boost current for the linear regulators’
output drives in the event bipolar NPN transistors (instead
of N-Channel MOSFETs) are employed as pass elements.
The voltage at this pin is monitored for POR purposes.
SS (Pin 12)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28µA current source, sets the soft-start
interval of the converter.
FAULT / RT (Pin 13)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (RT) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
Fs 200k Hz + R-5----T-×---(--1k---0----6--)
(RT to GND)
Conversely, connecting a resistor from this pin to VCC
reduces the switching frequency according to the following
equation:
Fs 200k Hz R-4----T-×---(--1k---0----7--)
(RT to 12V)
Nominally, the voltage at this pin is 1.26V. In the event of an
overvoltage or overcurrent condition, this pin is internally
pulled to VCC.
PGOOD (Pin 8)
PGOOD is an open collector output used to indicate the
status of the output voltages. This pin is pulled low when the
synchronous regulator output is not within ±10% of the
DACOUT reference voltage or when any of the other outputs
are below their undervoltage thresholds.
The PGOOD output is open for ‘11111’ VID code.
SD (Pin 9)
This pin shuts down all the outputs. A TTL-compatible, logic
level high signal applied at this pin immediately discharges
the soft-start capacitor, disabling all the outputs. Dedicated
internal circuitry insures the core output voltage does not go
negative during this process. When re-enabled, the IC
undergoes a new soft-start cycle. Left open, this pin is pulled
low by an internal pull-down resistor, enabling operation.
FIX (Pin 2)
Grounding this pin bypasses the internal resistor dividers
that set the output voltage of the 1.5V and 1.8V linear
regulators. This way, the output voltage of the two regulators
can be adjusted from 1.26V up to the input voltage (+3.3V or
+5V) by way of an external resistor divider connected at the
corresponding VSEN pin. The new output voltage set by the
external resistor divider can be determined using the
following formula:
VOUT
=
1.265 V
×
1
+
R-R----GO-----NU----DT--
where ROUT is the resistor connected from VSEN to the
output of the regulator, and RGND is the resistor connected
from VSEN to ground. Left open, the FIX pin is pulled high,
enabling fixed output voltage operation.
VID0, VID1, VID2, VID3, VID4 (Pins 7, 6, 5, 4 and 3)
VID0-4 are the TTL-compatible input pins to the 5-bit DAC.
The logic states of these five pins program the internal
voltage reference (DACOUT). The level of DACOUT sets the
microprocessor core converter output voltage, as well as the
corresponding PGOOD and OVP thresholds.
OCSET (Pin 23)
Connect a resistor from this pin to the drain of the respective
upper MOSFET. This resistor, an internal 200µA current
source, and the upper MOSFET’s on-resistance set the
converter overcurrent trip point. An overcurrent trip cycles
the soft-start function.
The voltage at this pin is monitored for POR purposes and
pulling this pin low with an open drain device will shutdown
the IC.
PHASE (Pin 26)
Connect the PHASE pin to the PWM converter’s upper
MOSFET source. This pin represents the gate drive return
current path and is used to monitor the voltage drop across
the upper MOSFET for overcurrent protection.
UGATE (Pin 27)
Connect UGATE pin to the PWM converter’s upper
MOSFET gate. This pin provides the gate drive for the upper
MOSFET.
LGATE (Pin 25)
Connect LGATE to the PWM converter’s lower MOSFET
gate. This pin provides the gate drive for the lower MOSFET.
COMP and FB (Pin 20 and 21)
COMP and FB are the available external pins of the PWM
converter error amplifier. The FB pin is the inverting input of the
6

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部品番号部品説明メーカ
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ISL6440A

Advanced PWM and Triple Linear Power Controller

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