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PDF ISL6307 Data sheet ( Hoja de datos )
| Número de pieza | ISL6307 | |
| Descripción | 6-Phase PWM Controller | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
March 9, 2006
ISL6307
FN9224.0
6-Phase PWM Controller with 8 Bit VID
Code Capable of Precision RDS(ON) or
DCR Differential Current
The ISL6307 controls microprocessor core voltage regulation
by driving up to 6 synchronous-rectified buck channels in
parallel. Multiphase buck converter architecture uses
interleaved timing to multiply channel ripple frequency and
reduce input and output ripple currents. Lower ripple results in
fewer components, lower component cost, reduced power
dissipation, and smaller implementation area.
Microprocessor loads can generate load transients with
extremely fast edge rates. The ISL6307 features a high
bandwidth control loop and ripple frequencies up to 6MHz to
provide optimal response to the transients.
Today’s microprocessors require a tightly regulated output
voltage position versus load current (droop). The ISL6307
senses current by utilizing patented techniques to measure
the voltage across the on resistance, RDS(ON), of the lower
MOSFETs or DCR, of the output inductor during the lower
MOSFET conduction intervals. Current sensing provides the
needed signals for precision droop, channel-current
balancing, and overcurrent protection. A programmable
internal temperature compensation function is implemented
to effectively compensate for the temperature coefficient of
the current sense element.
A unity gain, differential amplifier is provided for remote
voltage sensing. Any potential difference between remote
and local grounds can be completely eliminated using the
remote-sense amplifier. Eliminating ground differences
improves regulation and protection accuracy. The threshold-
sensitive enable input is available to accurately coordinate
the start up of the ISL6307 with any other voltage rail.
Dynamic-VID™ technology allows seamless on-the-fly VID
changes. The offset pin allows accurate voltage offset
settings that are independent of VID setting.
Ordering Information
PART NUMBER
TEMP. (°C)
PKG. DWG.
PACKAGE
#
ISL6307CRZ
(See Note)
0 to 70
48 Ld 7x7 QFN L48.7x7
(Pb-free)
ISL6307IRZ
(See Note)
-40 to 85 48 Ld 7x7 QFN L48.7x7
(Pb-free)
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
Features
• Precision Multiphase Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over Life, Load, Line and
Temperature
- Adjustable Precision Reference-Voltage Offset
• Precision RDS(ON) or DCR Current Sensing
- Accurate Load-Line Programming
- Accurate Channel-Current Balancing
- Differential Current Sense
• Microprocessor Voltage Identification Input
- Dynamic VID™ Technology
- 8-Bit VID Input with Selectable VR11 Code and
Extended VR10 Code at 6.25mV Step
- 0.5V to 1.600V operation range
• Threshold-Sensitive Enable Function for Power
Sequencing and VTT Enable
• Thermal Monitoring
• Programmable Temperature Compensation
• Overcurrent Protection
• Overvoltage Protection with OVP Output Indication
• 2, 3, 4, 5 or 6 Phase Operation
• Adjustable Switching Frequency up to 1MHz per Phase
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Dynamic VID™ is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6307
Typical Application - 6-Phase Buck Converter with RDS(ON) Sensing and Integrated TCOMP
+5V
VCC
BOOT
UGATE
EN
PWM
GND
ISL6605
DRIVER
PHASE
LGATE
VIN
+5V
FB
IDROOP
VDIFF
COMP REF
DAC
VTT
VR_RDY
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VRSEL
OVP
VSEN
RGND
EN_VTT
VCC
GND
ISL6307
PWM6
ISEN6-
ISEN6+
PWM4
ISEN4-
ISEN4+
PWM2
ISEN2-
ISEN2+
IOUT
R IOUT
PWM1
ISEN1-
ISEN1+
PWM3
ISEN3-
VR_FAN
VR_HOT
ISEN3+
PWM5
ISEN5-
ISEN5+
TM EN_PWR
+5V TCOMP OFS FS SS
+5V
ROFS
RT
R SS
+12V
NTC
+5V
VCC
BOOT
UGATE
EN
PWM
GND
ISL6605
DRIVER
PHASE
LGATE
+5V
VCC
BOOT
UGATE
EN
PWM
GND
ISL6605
DRIVER
PHASE
LGATE
+5V
VCC
BOOT
UGATE
EN
PWM
GND
ISL6605
DRIVER
PHASE
LGATE
+5V
VCC
BOOT
UGATE
EN
PWM
GND
ISL6605
DRIVER
PHASE
LGATE
+5V
VCC
BOOT
UGATE
EN
PWM
GND
ISL6605
DRIVER
PHASE
LGATE
VIN
VIN
VIN
VIN
VIN
µP
LOAD
5 FN9224.0
March 9, 2006
5 Page 
ISL6307
Functional Pin Description
VCC - Supplies all the power necessary to operate the chip.
The controller starts to operate when the voltage on this pin
exceeds the rising POR threshold and shuts down when the
voltage on this pin drops below the falling POR threshold.
Connect this pin directly to a +5V supply.
GND - Bias and reference ground for the IC. The bottom
metal base of ISL6307 is the GND.
EN_PWR - This pin is a threshold-sensitive enable input for
the controller. Connecting the 12V supply to EN_PWR
through an appropriate resistor divider provides a means to
synchronize power-up of the controller and the MOSFET
driver ICs. When EN_PWR is driven above 0.875V, the
ISL6307 is active depending on status of EN_VTT, the
internal POR, and pending fault states. Driving EN_PWR
below 0.745V will clear all fault states and prime the ISL6307
to soft-start when re-enabled.
EN_VTT - This pin is another threshold-sensitive enable
input for the controller. It’s typically connected to VTT output
of VTT voltage regulator in the computer mother board.
When EN_VTT is driven above 0.875V, the ISL6307 is active
depending on status of ENLL, the internal POR, and pending
fault states. Driving EN_VTT below 0.745V will clear all fault
states and prime the ISL6307 to soft-start when re-enabled.
FS - Use this pin to set up the desired switching frequency. A
resistor, placed from FS to ground will set the switching fre-
quency. The relationship between the value of the resistor
and the switching frequency will be described by an approxi-
mate Equation 40.
SS - Use this pin to set up the desired start-up oscillator fre-
quency. A resistor, placed from SS to ground will set up the
soft-start ramp rate. The relationship between the value of the
resistor and the soft-start ramp up time will be described by
an approximate Equation 14.
VID7, VID6, VID5, VID4, VID3, VID2, VID1 and VID0 -
These are the inputs to the internal DAC that provides the
reference voltage for output regulation. Connect these pins
either to open-drain outputs with or without external pull-up
resistors or to active pull-up outputs. VID7-VID0 have 40µA
internal pull-up current sources that diminish to zero as the
voltage rises above the logic-high level. These inputs can be
pulled up as high as VCC plus 0.3V.
When a VID code causes a shut-off, the controller needs to
be reset before it will start again.
VRSEL - Use this pin to select Internal VID code. when it is
connected to GND, the extended VR10 code is selected.
When it’s floated or pulled to high, the VR11 code is selected.
This input can be pulled up as high as VCC plus 0.3V.
VDIFF, VSEN, and RGND - VSEN and RGND form the
precision differential remote-sense amplifier. This amplifier
converts the differential voltage of the remote output to a
single-ended voltage referenced to local ground. VDIFF is
the amplifier’s output and the input to the regulation and
protection circuitry. Connect VSEN and RGND to the sense
pins of the remote load.
FB and COMP - Inverting input and output of the error
amplifier respectively. FB is connected to VDIFF through a
resistor. A negative current, proportional to output current is
present on the FB pin. A properly sized resistor between
VDIFF and FB sets the load line (droop). The droop scale
factor is set by the ratio of the ISEN resistors and the lower
MOSFET RDS(ON). COMP is tied back to FB through an
external R-C network to compensate the regulator.
DAC and REF - The DAC output pin is the output of the
precision internal DAC reference. The REF input pin is the
positive input of the Error Amp. In typical applications, a 1kΩ,
1% resistor is used between DAC and REF to generate a
precise offset voltage. This voltage is proportional to the
offset current determined by the offset resistor from OFS to
ground or VCC. A capacitor is used between REF and
ground to smooth the voltage transition during Dynamic
VID™ operations.
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6 - Pulse-
width modulation outputs. Connect these pins to the PWM
input pins of the Intersil driver IC. The number of active
channels is determined by the state of PWM3, PWM4,
PWM5 and PWM 6. Tie PWM3 to VCC to configure for
2-phase operation. Tie PWM4 to VCC to configure for
3-phase operation. Tie PWM5 to VCC to configure for
4-phase operation. Tie PWM6 to VCC to configure for
5-phase operation.
ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-;
ISEN4+, ISEN4-; ISEN5+, ISEN5-; ISEN6+, ISEN6- - The
ISEN+ and ISEN- pins are current sense inputs to individual
differential amplifiers. The sensed current is used as a
reference for channel balancing, protection, and regulation.
Inactive channels should have their respective current sense
inputs left open (for example, for 3-phase operation open
ISEN4+).
For DCR sensing, connect each ISEN- pin to the node
between the RC sense elements. Tie the ISEN+ pin to the
other end of the sense capacitor through a resistor, RISEN.
The voltage across the sense capacitor is proportional to the
inductor current. The sense current is proportional to the
output current, and scaled by the DCR of the inductor and
RISEN.
When configured for RDS(ON) current sensing, the ISEN1-,
ISEN2-, ISEN3-, ISEN4-, ISEN5-, ISEN6- pins are grounded
at the lower MOSFET sources. The ISEN1+, ISEN2+,
ISEN3+, ISEN4+, ISEN5+, ISEN6+ pins are then held at a
virtual ground, such that a resistor connected between them,
and the drain terminal of the associated lower MOSFET, will
carry a current proportional to the current flowing through
that channel. The current is determined by the negative
11 FN9224.0
March 9, 2006
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISL6307.PDF ] | |
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