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PDF ISL6271A Data sheet ( Hoja de datos )
| Número de pieza | ISL6271A | |
| Descripción | Integrated XScale Regulator | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
October 8, 2004
ISL6271A
FN9171.1
Integrated XScale Regulator
The ISL6271A is a versatile power management IC (PMIC)
designed for the Xscale type of processors. The device
integrates three regulators, two fault indicators and an I2C
bus for communication with a host microprocessor. Two of
the three regulators function as low power, low drop out
regulators, designed to power SRAM and phase-lock loop
circuitry internal to the Xscale processor. The third regulator
uses a proprietary switch-mode topology to power the
processor core and facilitate Dynamic Voltage Management
(DVM), as defined by Intel.
Since power dissipation inside a microprocessor is
proportional to the square of the core voltage, Intel XScale
processors implement DVM as a means to more efficiently
utilize battery capacity. To support this power saving
architecture, the ISL6271A integrates an I2C bus for
communication with the host processor. The processor, acting
as the bus master, transmits a “voltage level” and “voltage
slew rate” to the ISL6271A appropriate to the processing
requirements; higher core voltages support higher operating
frequencies and code execution. The bus is fully compliant
with the Phillips® I2C protocol and supports both standard
and fast data transmission modes. Alternatively, the output of
the core regulator can be programmed in 50mV increments
from 0.85V to 1.6V using the input Voltage ID (VID) pins. All
three regulators share a common enable pin and are
protected against overcurrent, over temperature and
undervoltage conditions. When disabled via the enable pin,
the ISL6271A enters a low power state that can be used to
conserve battery life while maintaining the last programmed
VID code and slew rate. An integrated soft-start circuit
transitions the ISL6271A output voltages to their default
values at a rate determined by an external soft-start capacitor.
Pinout
ISL6271A (4x4 QFN) TOP VIEW
20 19 18 17 16
VCC 1
VIDEN 2
SCL/VID0 3
SDA/VID1 4
VID2 5
15 LVCC
14 VPLL
13 VSRAM
12 FB
11 VOUT
6 7 8 9 10
Features
• Three Voltage Regulators (1 Buck, 2 LDOs)
• High-Efficiency, fully-Integrated synchronous buck
regulator with DVM
• 800mA DC output current for the buck regulator
• Proprietary ‘Synthetic Ripple’ Control Topology
• Greater than 1MHz Switching Frequency
• Diode emulation for light load efficiency
• I2C Interface Module for DVM from 0.85V to 1.6V
• Optional fixed 4-bit VID-control in lieu of DVM
• Small Output Inductor and Capacitor
• Battery Fault signal
• Input Supply Voltage Range: 2.76V-5.5V
• 4x4 mm QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-free Available (RoHS Compliant)
Applications
• PDA
• Cell Phone
• Tablet Devices
• Embedded Processors
Related Literature
• Technical Brief TB379 “Thermal Characterization of
Packaged Semiconductor Devices”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages“
• Application Note AN1139 “Setup Instruction for the
ISL6271 Evaluation Kit”
Ordering Information
PART NUMBER*
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6271ACR
-25 to 85 20 Ld 4x4 QFN L20.4x4
ISL6271ACRZ (Note)
-25 to 85
20 Ld 4x4 QFN L20.4x4
(Pb-free)
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004. All Rights Reserved
Intel® is a registered trademark of Intel Corporation. All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6271A
Typical Operating Performance
Test results from the Intersil ISL6271A Customer Reference Board (CRB). Output filter on switcher made up of a 4.7µH drumcore with 100mΩ of
DCR and an output capacitance of 10µF. X5R; Rcomp = 50kΩ, Vin = 3.6V unless otherwise noted.
100%
95%
90%
85%
80%
75%
70%
65%
60%
0
Vo=1.6V
Vo=1.3V
200 400 600
Io (mA)
FIGURE 3. EFFICIENCY (Vin = 3.6V)
800
1.094
1.093
Io = 10mA
1.092
Io = 25mA
1.091
1.09
1.089
Iout = 55mA
1.088
1.087
1.086
Iout = 85mA
1.085
1.7 2.5 3.5
INPUT VOLTAGE
FIGURE 4. VSRAM LINE-LOAD REGULATION
1.309
1.308
1.307
Io = 5mA
Io = 20mA
1.306
1.305
1.304
1.303
Iout = 55mA
1.302
Iout = 65mA
1.301
1.7
2.5
3.5
INPUT VOLTAGE
FIGURE 5. SWITCHING REGULATOR EFFICIENCY
VOUT
PHASE
IOUT
50mA to 260mA load step on VOUT.
Top: Output voltage, 50mV/DIV; Phase node, 5V/DIV.;
Inductor current, 200mA/DIV, 2µs/DIV
FIGURE 6. DCM TO CCM
5
Top: phase node output voltage ripple, 10mV/DIV.
Bottom: Inductor current, 100mA/DIV, 1µs/DIV
FIGURE 7. CCM TO CCM
FN9171.1
5 Page 
ISL6271A
I2C SEND BYTE PROTOCOL
S 0 00 1 10 0 00 X
START A6 A5 A4 A3 A2 A1 A0 W A
SLAVE ADDRESS
SLEW
VOLTAGE
SET
X D5 D4 D3 D2 D1 D0 0 P
A STOP
COMMAND BYTE
I2C RECEIVE BYTE PROTCOL
S 0 0 0 1 1 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1 P
START A6 A5 A4 A3 A2 A1 A0 W A
A STOP
SLAVE ADDRESS
DATA BYTE
FIGURE 18. INTERFACE BIT DEFINITION AND PROTOCOL
VID and Slew Rate Program Register
In a typical XScale configuration, the processor’s “Power
Manager” will issue the voltage and slew rate commands to
the ISL6271A over its PWR_ I2C bus after the ISL6271A
acknowledges its address. The data byte is composed of two
pieces of ‘set’ information: The prescribed voltage level
embedded in bits D0-D3, and the prescribed transition slew
rate (from the previous voltage to the target voltage)
embedded in bits D4-D5. Each set of bits is transmitted MSB
first. This protocol is depicted in Figure 18.
Application Guidelines
Every effort should be made to place the ISL6271A as close
as possible to the processor, with the orientation favoring the
shortest voltage routing. The regulator input capacitors
should be located close to their respective input pins.
All output capacitors should be kept close to their respective
output pins with the ground pins connected immediately to
the ground plane. Care should be taken to avoid routing
sensitive, high impedance signals near the PHASE pin on
the controller, and the attendant PCB traces.
To minimize switching noise, it is important to keep the loop
area associated with the phase node and output filter as
short as possible. It is also important that the input voltage
decoupling capacitor C7 be located as close to the PVCC
pin as possible and that it has a low impedance return path
to the PGND pin. In general a good approach to layout is to
consider how switching current flows in a circuit, and to
minimize the loop area associated with this current. In the
case of the switching regulator, current flows from C7
through the internal upper P-MOSFET, to the load through
the output filter and back to the PGND pin. To maximize the
effectiveness of any decoupling capacitor, minimize the
parasitic inductance between the capacitor and the circuit it
is decoupling. Notice that Figure 19 illustrates the SIGNAL
ground with RED highlighting. All components associated
with these terminals should be tied together first. Be sure to
make only one connection between this net and the PGND
pin to avoid ground loops and noise injection points into
sensitive analog circuitry.
BBAT ≤ VCC
COIN CELL
BACK-UP
Li-ion
4.2V
TO
2.60V
R7, 10Ω
C3
C7 0.1µF
10µF
1.8V
OR 2.5V
C2
2.2µF
C4
10nF
X7R
ISL6271A
BBAT
PVCC
SCL/VID0
SDA/VID1
VCC
PGOOD
BFLT#
LVCC
EN
VSRAM
SOFT
VIDEN
VID2
VID3
GND
VPLL
FB
VOUT
PHASE
PGND
Single point connection
between PGND and GND pins
5kΩ 5kΩ 5kΩ
C8
2.2µF
X5R
Rcomp, 50K
C5
2.2µF
X5R
XScale µP
PWR_I2C
FAULT
REG. EN
VCC_SRAM
VCC_PLL
VCC_CORE
L1
4.7µH
C6
10µF
X5R
Power ground. Minimize the loop area associated
with L1, C6 and the PHASE and PGND pins.
FIGURE 19. TYPICAL APPLICATION CIRCUIT
11 FN9171.1
11 Page | ||
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