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PDF ISL6752 Data sheet ( Hoja de datos )
| Número de pieza | ISL6752 | |
| Descripción | ZVS Full-Bridge Current-Mode PWM | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
October 31, 2008
ISL6752
FN9181.3
ZVS Full-Bridge Current-Mode PWM with
Adjustable Synchronous Rectifier Control
The ISL6752 is a high-performance, low-pin-count alternative
zero-voltage switching (ZVS) full-bridge PWM controller. Like
Intersil’s ISL6551, it achieves ZVS operation by driving the
upper bridge FETs at a fixed 50% duty cycle while the lower
bridge FETs are trailing-edge modulated with adjustable
resonant switching delays. Compared to the more familiar
phase-shifted control method, this algorithm offers equivalent
efficiency and improved overcurrent and light-load performance
with less complexity in a lower pin count package.
The ISL6752 features complemented PWM outputs for
synchronous rectifier (SR) control. The complemented
outputs may be dynamically advanced or delayed relative to
the PWM outputs using an external control voltage.
This advanced BiCMOS design features precision deadtime
and resonant delay control, and an oscillator adjustable to
2MHz operating frequency. Additionally, Multi-Pulse
Suppression ensures alternating output pulses at low duty
cycles where pulse skipping may occur.
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE PKG.
(Pb-free) DWG. #
ISL6752AAZA* ISL 6752AAZ -40 to +105 16 Ld QSOP M16.15A
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Adjustable Resonant Delay for ZVS Operation
• Synchronous Rectifier Control Outputs with Adjustable
Delay/Advance
• Current-Mode Control
• 3% Current Limit Threshold
• Adjustable Deadtime Control
• 175µA Start-up Current
• Supply UVLO
• Adjustable Oscillator Frequency Up to 2MHz
• Internal Over-Temperature Protection
• Buffered Oscillator Sawtooth Output
• Fast Current Sense to Output Delay
• Adjustable Cycle-by-Cycle Peak Current Limit
• 70ns Leading Edge Blanking
• Multi-Pulse Suppression
• Pb-Free (RoHS Compliant)
Applications
• ZVS Full-Bridge Converters
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
• Industrial Power Systems
Pinout
ISL6752
(16 LD QSOP)
TOP VIEW
VADJ 1
VREF 2
VERR 3
CTBUF 4
RTD 5
RESDEL 6
CT 7
CS 8
16 VDD
15 OUTLL
14 OUTLR
13 OUTUL
12 OUTUR
11 OUTLLN
10 OUTLRN
9 GND
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6752
Absolute Maximum Ratings (Note 2)
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
OUTxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF + 0.3V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1A
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . 9VDC to 16VDC
Thermal Information
Thermal Resistance Junction to Ambient (Typical)
θJA (°C/W)
16 Ld QSOP (Note 1). . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. All voltages are with respect to GND.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2
and “Typical Application - High Voltage Input Primary Side Control ZVS Full-Bridge Converter” on page 3 and
“Typical Application - High Voltage Input Secondary Side Control ZVS Full-Bridge Converter” on page 4.
9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, TA = -40°C to +105°C, Typical values are at TA = +25°C;
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY VOLTAGE
Supply Voltage
- - 20 V
Start-Up Current, IDD
Operating Current, IDD
UVLO START Threshold
VDD = 5.0V
RLOAD, COUT = 0
-
-
8.00
175
11.0
8.75
400 µA
15.5 mA
9.00 V
UVLO STOP Threshold
6.50 7.00 7.50 V
Hysteresis
- 1.75 - V
REFERENCE VOLTAGE
Overall Accuracy
Long Term Stability
Operational Current (Source)
IVREF = 0mA to 10mA
TA = +125°C, 1000 hours (Note 3)
4.850
-
-10
5.000
3
-
5.150
-
-
V
mV
mA
Operational Current (Sink)
5 - - mA
Current Limit
VREF = 4.85V
-15
-
-100
mA
CURRENT SENSE
Current Limit Threshold
VERR = VREF
0.97 1.00 1.03 V
CS to OUT Delay
Excl. LEB (Note 3)
- 35 50 ns
Leading Edge Blanking (LEB) Duration
(Note 3)
50 70 100 ns
CS to OUT Delay + LEB
CS Sink Current Device Impedance
Input Bias Current
CS to PWM Comparator Input Offset
PULSE WIDTH MODULATOR
TA = +25°C
VCS = 1.1V
VCS = 0.3V
TA = +25°C
- - 130 ns
- - 20 Ω
-6.00
-
-2.00
µA
65 80 95 mV
VERR Pull-Up Current Source
VERR = 2.50V
0.80 1.00 1.30 mA
VERR VOH
Minimum Duty Cycle
ILOAD = 0mA
VERR < 0.6V
4.20
-
-
-
-V
0%
5 FN9181.3
October 31, 2008
5 Page 
ISL6752
Since the peak current limit threshold is 1.00V, the total
current feedback signal plus the external ramp voltage must
sum to this value.
Ve + VCS = 1
(EQ. 15)
Substituting Equations 13 and 14 into Equation 15 and
solving for RCS yields Equation 16:
RCS
=
N-----P-----⋅---N-----C----T-
NS
⋅
-------------------------1---------------------------
IO
+
V-----O--
LO
tS
⎛
W⎝
1π--
+
D-2--⎠⎞
Ω
(EQ. 16)
For simplicity, idealized components have been used for this
discussion, but the effect of magnetizing inductance must be
considered when determining the amount of external ramp
to add. Magnetizing inductance provides a degree of slope
compensation to the current feedback signal and reduces
the amount of external ramp required. The magnetizing
inductance adds primary current in excess of what is
reflected from the inductor current in the secondary.
ΔIP
=
V-----I--N-----⋅---D-----t--S----W---
Lm
A
(EQ. 17)
where VIN is the input voltage that corresponds to the duty
cycle D and Lm is the primary magnetizing inductance. The
effect of the magnetizing current at the current sense
resistor, RCS, is expressed in Equation 18:
ΔVCS
=
Δ-----I--P-----⋅---R----C----S--
NCT
V
(EQ. 18)
If ΔVCS is greater than or equal to Ve, then no additional slope
compensation is needed and RCS becomes Equation 19:
RCS
=
------------------------------------------------------------N----C----T-------------------------------------------------------------
N-----S--
NP
⋅
⎛
⎜
⎝
IO
+
D-----t--S----W---
2LO
⋅
⎛
⎜
⎝
VI
N
⋅
N-----S--
NP
–
⎞⎞
VO⎠⎟
⎟
⎠
+
-V----I--N-----⋅---D-----t--S----W---
Lm
(EQ. 19)
If ΔVCS is less than Ve, then Equation 16 is still valid for the
value of RCS, but the amount of slope compensation added
by the external ramp must be reduced by ΔVCS.
Adding slope compensation may be accomplished in the
ISL6752 using the CTBUF signal. CTBUF is an amplified
representation of the sawtooth signal that appears on the CT
pin. It is offset from ground by 0.4V and is 2x the peak-to-peak
amplitude of CT (0.4V to 4.4V). A typical application sums this
signal with the current sense feedback and applies the result
to the CS pin, as shown in Figure 6.
R9
R6
RCS
1
2 ISL6752
3
4 CTBUF
5
6
7
8 CS
C4
16
15
14
13
12
11
10
9
FIGURE 6. ADDING SLOPE COMPENSATION
Assuming the designer has selected values for the RC filter
placed on the CS pin, the value of R9 required to add the
appropriate external ramp can be found by superposition.
Ve – ΔVCS
=
-(--D-----(--V----C-----T---B----U----F-----–----0----.-4----)----+-----0---.--4---)----⋅---R-----6-
R6 + R9
V
(EQ. 20)
Rearranging to solve for R9 yields Equation 21:
R9
=
(---D-----(--V----C-----T---B----U----F-----–----0----.-4----)----–----V----e-----+-----Δ----V----C----S-----+-----0----.-4----)----⋅---R----6--
Ve – ΔVCS
Ω
(EQ. 21)
The value of RCS determined in Equation 16 must be
rescaled so that the current sense signal presented at the
CS pin is that predicted by Equation 14. The divider created
by R6 and R9 makes this necessary.
R′CS
=
R-----6-----+-----R-----9--
R9
⋅
RCS
(EQ. 22)
Example:
VIN = 280V
VO = 12V
LO = 2.0µH
Np/Ns = 20
Lm = 2mH
IO = 55A
Oscillator Frequency, FSW = 400kHz
Duty Cycle, D = 85.7%
NCT = 50
R6 = 499Ω
Solve for the current sense resistor, RCS, using Equation 16.
RCS = 15.1Ω.
11 FN9181.3
October 31, 2008
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ISL6752.PDF ] | |
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