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PDF ISL6597 Data sheet ( Hoja de datos )
| Número de pieza | ISL6597 | |
| Descripción | Dual Synchronous Rectified MOSFET Drivers | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
November 22, 2006
ISL6597
FN9165.0
Dual Synchronous Rectified MOSFET
Drivers
The ISL6597 integrates two ISL6596 drivers and is
optimized to drive two independent power channels in a
synchronous-rectified buck converter topology. These
drivers, combined with an Intersil multiphase PWM
controller, form a complete high efficiency voltage regulator
solution.
The IC is biased by a single low voltage supply (5V),
minimizing driver switching losses in high MOSFET gate
capacitance and high switching frequency applications.
Each driver is capable of driving a 3nF load with less than
10ns rise/fall time. Bootstrapping of the upper gate driver is
implemented via an internal low forward drop diode,
reducing implementation cost, complexity, and allowing the
use of higher performance, cost effective N-Channel
MOSFETs. Adaptive shoot-through protection is integrated
to prevent both MOSFETs from conducting simultaneously.
The ISL6597 features 4A typical sink current for the lower
gate driver, enhancing the lower MOSFET gate hold-down
capability during PHASE node rising edge, preventing power
loss caused by the self turn-on of the lower MOSFET due to
the high dV/dt of the switching node.
The ISL6597 also features an input that recognizes a high-
impedance state, working together with Intersil multi-phase
3.3V or 5V PWM controllers to prevent negative transients
on the controlled output voltage when operation is
suspended. This feature eliminates the need for the schottky
diode that may be utilized in a power system to protect the
load from negative output voltage damage.
Ordering Information
PART
NUMBER
(Note)
ISL6597CRZ
TEMP.
PART RANGE
MARKING (°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
65 97CRZ 0 to +70 16 Ld 4x4 QFN L16.4x4
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• 5V Quad N-Channel MOSFET Drives for Two
Synchronous Rectified Bridges
• Adaptive Shoot-Through Protection
• Programmable Deadtime for Efficiency Optimization
• Diode Emulation for Efficiency and Pre-Biased Startup
• 0.4Ω On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency
- Fast Output Rise and Fall
- Ultra Low Tri-State Hold-Off Time (20ns)
• Low VF Internal Bootstrap Diode
• Low Bias Supply Current
• Support 3.3V and 5V PWM Input
• Enable Input and Power-On Reset
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline
- Near Chip-Scale Package Footprint; Improves PCB
Utilization and Thinner in Profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Core Voltage Supplies for Intel® and AMD®
Microprocessors
• High Frequency Low Profile High Efficiency DC/DC
Converters
• High Current Low Voltage DC/DC Converters
• Synchronous Rectification for Isolated Power Supplies
Related Literature
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packages”
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
AMD® is a registered trademark of Advanced Micro Devices, Inc. All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6597
Electrical Specifications These specifications apply for TA = 0°C to +70°C, unless otherwise noted (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP
LGATE Fall Time
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
Tri-state to UG/LG Rising Propagation Delay
OUTPUT (Note 3)
tFL
tPDLU
tPDLL
tPDHU
tPDHL
tPTS
VVCC = 5V, 3nF Load
VVCC = 5V, Unloaded,
VVCC = 5V, Unloaded,
VVCC = 5V, Unloaded,
VVCC = 5V, Unloaded,
VVCC = 5V, Unloaded
- 4.0
- 18
- 25
- 18
- 23
- 30
Upper Drive Source Resistance
RUG_SRC 250mA Source Current
Upper Drive Sink Resistance
RUG_SNK 250mA Sink Current
Lower Drive Source Resistance
RLG_SRC 250mA Source Current
Lower Drive Sink Resistance
RLG_SNK 250mA Sink Current
NOTE:
3. Guaranteed by Characterization. Not 100% tested in production.
- 1.0
- 1.0
- 1.0
- 0.4
MAX
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
2.5 Ω
2.5 Ω
2.5 Ω
1.0 Ω
Functional Pin Description
PACKAGE PIN
PIN # SYMBOL
FUNCTION
1 GND Bias and reference ground. All signals are referenced to this node.
2 LGATE1 Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.
3 PVCC This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor from
this pin to PGND.
4 EN Enable input pin. Connect this pin high to enable and low to disable the driver.
5 PGND It is the power ground return of both low gate drivers.
6 LGATE2 Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.
7 VCTRL This pin sets the PWM logic threshold. Connect this pin to 3.3V source for 3.3V PWM input and pull it to 5V source for
5V PWM input.
8 PHASE2 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This pin
provides a return path for the upper gate drive.
9 UGATE2 Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.
10 BOOT2 Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this pin
and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal
Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
11 BOOT1 Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this pin
and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal
Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
12 UGATE1 Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.
13 PHASE1 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This pin
provides a return path for the upper gate drive.
14 VCC Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic
capacitor from this pin to GND.
15 PWM1 The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during operation,
see the tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the
controller.
16 PWM2 The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during operation,
see the tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the
controller.
17 PAD Connect this pad to the power ground plane (PGND) via thermally enhanced connection.
5 FN9165.0
November 22, 2006
5 Page | ||
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| PDF Descargar | [ Datasheet ISL6597.PDF ] | |
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