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PDF ISL6209 Data sheet ( Hoja de datos )
| Número de pieza | ISL6209 | |
| Descripción | High Voltage Synchronous Rectified Buck MOSFET Driver | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
March 23, 2007
ISL6209
FN9132.2
High Voltage Synchronous Rectified Buck
MOSFET Driver
The ISL6209 is a high frequency, dual MOSFET driver,
optimized to drive two N-Channel power MOSFETs in a
synchronous-rectified buck converter topology in mobile
computing applications. This driver, combined with an Intersil
Multi-Phase Buck PWM controller, such as ISL6216, ISL6244,
and ISL6247, forms a complete single-stage core-voltage
regulator solution for advanced mobile microprocessors.
The ISL6209 features 4A typical sink current for the lower gate
driver. The 4A typical sink current is capable of holding the
lower MOSFET gate during the PHASE node rising edge to
prevent the shoot-through power loss caused by the high dv/dt
of the PHASE node. The operation voltage matches the 30V
breakdown voltage of the MOSFETs commonly used in mobile
computer power supplies.
The ISL6209 also features a three-state PWM input that,
working together with most of Intersil multiphase PWM
controllers, will prevent a negative transient on the output
voltage when the output is being shut down. This feature
eliminates the Schottky diode, that is usually seen in a
microprocessor power system for protecting the
microprocessor, from reversed-output-voltage damage.
The ISL6209 has the capacity to efficiently switch power
MOSFETs at frequencies up to 2MHz. Each driver is capable of
driving a 3000pF load with a 8ns propagation delay and less
than a 10ns transition time. This product implements
bootstrapping on the upper gate with an internal bootstrap
Schottky diode, reducing implementation cost, complexity, and
allowing the use of higher performance, cost effective
N-Channel MOSFETs. Programmable dead-time with gate
threshold monitoring is integrated to prevent both MOSFETs
from conducting simultaneously.
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
• Technical Brief TB447 “Guidelines for Preventing Boot-to-
Phase Stress on Half-Bridge MOSFET Driver ICs”
Features
• Drives Two N-Channel MOSFETs
• Shoot-Through Protection
- Active gate threshold monitoring
- Programmable dead-time
• 30V Operation Voltage
• 0.4Ω On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency
- Fast output rise time
- Propagation delay 8ns
• Three-State PWM Input for Power Stage Shutdown
• Internal Bootstrap Schottky Diode
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Core Voltage Supplies for Intel and AMD® Mobile
Microprocessors
• High Frequency Low Profile DC/DC Converters
• High Current Low Output Voltage DC/DC Converters
• High Input Voltage DC/DC Converter
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
ISL6209CB* ISL6209CB -10 to +100 8 Ld SOIC
ISL6209CBZ* ISL6209CBZ -10 to +100 8 Ld SOIC
(Note)
(Pb-free)
ISL6209CR* 209C
-10 to +100 8 Ld 3x3 QFN
*Add “-T” suffix for tape and reel.
PKG.
DWG. #
M8.15
M8.15
L8.3x3
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005, 2007. All Rights Reserved. Intel® is a registered trademark of Intel Corporation.
AMD® is a registered trademark of Advanced Micro Devices, Inc. All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6209
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
LGATE Turn-On Propagation Delay
tPDHLGATE VVCC = 5V, Outputs Unloaded,
DELAY = VCC
10 20 30 ns
OUTPUT
Upper Drive Source Resistance
RUGATE 500mA Source Current
Upper Driver Source Current (Note 5)
IUGATE VUGATE-PHASE = 2.5V
Upper Drive Sink Resistance
RUGATE 500mA Sink Current
Upper Driver Sink Current (Note 5)
IUGATE VUGATE-PHASE = 2.5V
Lower Drive Source Resistance
RLGATE 500mA Source Current
Lower Driver Source Current (Note 5)
ILGATE VLGATE = 2.5V
Lower Drive Sink Resistance
RLGATE 500mA Sink Current
Lower Driver Sink Current (Note 5)
ILGATE VLGATE = 2.5V
NOTE:
5. Guaranteed by characterization, not 100% tested in production.
- 1.0 2.5 Ω
- 2.0 -
A
- 1.0 2.5 Ω
- 2.0 -
A
- 1.0 2.5 Ω
- 2.0 -
A
- 0.4 1.0 Ω
- 4.0 -
A
Functional Pin Description
UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)
The UGATE pin is the upper gate drive output. Connect to
the gate of high-side power N-Channel MOSFET.
BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)
BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PWM (Pin 3 for SOIC-8, Pin 2 for QFN)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller. In
addition, place a 500kΩ resistor to ground from this pin. This
allows for proper three-state operation under all start-up
conditions.
GND (Pin 4 for SOIC-8, Pin 3 for QFN)
GND is the ground pin. All signals are referenced to this
node.
LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
VCC (Pin 6 for SOIC-8, Pin 5 for QFN)
Connect the VCC pin to a +5V bias supply. Place a high
quality bypass capacitor from this pin to GND.
DELAY (Pin 7 for SOIC-8, Pin 6 for QFN)
The DELAY pin sets the dead-time between gate switching
for the ISL6209. Connect a resistor to GND from this pin to
adjust the dead-time, refer to Figure 4. Tie this pin to VCC to
disable the delay circuitry. See Shoot-Through Protection
section for more detail.
PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)
Connect the PHASE pin to the source of the upper MOSFET
and the drain of the lower MOSFET. This pin provides a
return path for the upper gate driver.
Description
Operation
Designed for speed, the ISL6209 dual MOSFET driver controls
both high-side and low-side N-Channel FETs from one
externally provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [tPDLLGATE], the lower gate begins to fall. Typical fall
times [tFLGATE] are provided in the Electrical Specifications
section. Adaptive shoot-through circuitry monitors the
LGATE voltage and determines the upper gate delay time
[tPDHUGATE], based on how quickly the LGATE voltage
drops below 1V. This prevents both the lower and upper
MOSFETs from conducting simultaneously, or shoot-
through. Once this delay period is completed, the upper gate
drive begins to rise [tRUGATE], and the upper MOSFET
turns on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [tPDLUGATE] is encountered before the
upper gate begins to fall [tFUGATE]. Again, the adaptive
5
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet ISL6209.PDF ] | |
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