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ISL6173 の電気的特性と機能

ISL6173のメーカーはIntersil Corporationです、この部品の機能は「Dual Low Voltage Hot Swap Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6173
部品説明 Dual Low Voltage Hot Swap Controller
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL6173 Datasheet, ISL6173 PDF,ピン配置, 機能
®
Data Sheet
January 3, 2006
ISL6173
FN9186.3
Dual Low Voltage Hot Swap Controller
This IC targets dual voltage hot swap applications across the
+2.5V to +3.3V (nominal) bias supply voltage range with a
second lower voltage rail down to less than 1V. It features a
charge pump for driving external N-Channel MOSFETs,
regulated current protection and duration, output undervoltage
monitoring and reporting, optional latch-off or retry response,
and adjustable soft-start.
The current regulation level (CR) for each rail is set by two
external resistors and each CR duration is set by an external
capacitor on the TIM pin. After the CR duration has expired
the IC then quickly pulls down the associated GATE(s)
output turning off its external FET(s). The ISL6173 offers a
latched output or indefinite auto retry mode of operation.
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6173DRZA ISL6173DRZ 0 to +85 28 Ld 5x5 QFN L28.5x5
ISL6173DRZA-T ISL6173DRZ 0 to +85 28 Ld 5x5 QFN L28.5x5
Tape & Reel
ISL6173EVAL3 Evaluation Platform
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Pinout
ISL6173 (28 LD QFN) TOP VIEW
Features
• Fast Current Regulation amplifier quickly responds to
overcurrent fault conditions
• Less than 1µs response Time to Dead Short
• Programmable Current Regulation Level and Duration
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
• Overcurrent Circuit Breaker and Fault Isolation functions
• Adjustable Current Regulation Threshold as low as 20mV
• Selectable Latch-off or Auto Retry Response to Fault
conditions
• Adjustable voltage ramp-up for In-rush Protection During
Turn-On
• Rail Independent Control, Monitoring and Reporting I/O
• Dual Supply Hot Swap Power Distribution Control to <1V
• Charge Pump Allows the use of N-Channel MOSFETs
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Power Supply Sequencing, Distribution and Control
• Hot Swap/Electronic Breaker Circuits
V1(in)
Rsns1
V1(out)
28 27 26 25 24 23 22
SNS1 1
21 SNS2
VO1 2
20 VO2
SS1 3
19 SS2
GT1 4
18 GT2
FLT1 5
17 FLT2
PG1 6
16 PG2
CT1 7
15 CT2
8 9 10 11 12 13 14
EN1 EN2
RTR/LTCH
BIAS
CPQ+
VS1
SNS1
GT1 VO1
UV1
PG1
FLT1
SS1
CPQ-
CPVDD
ISL6173
OCREF
SS2
FLT2
PGND
PG2
GND
UV2
CT1 CT2 VS2 SNS2 GT2 VO2
V2(in)
Rsns2
FIGURE 1. TYPICAL APPLICATION
V2(OUT)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL6173 pdf, ピン配列
Pinout
ISL6173
28 LEAD QFN
TOP VIEW
28 27 26 25 24 23 22
SNS1 1
21 SNS2
VO1 2
20 VO2
SS1 3
19 SS2
GT1 4
18 GT2
FLT1 5
17 FLT2
PG1 6
16 PG2
CT1 7
15 CT2
8 9 10 11 12 13 14
Pin Descriptions
PIN NAME
FUNCTION
DESCRIPTION
1 SNS1 Current Sense Input This pin is connected to the current sense resistor and control MOSFET Drain node. It provides
current sense signal to the internal comparator and amplifier in conjunction with VS1 pin.
2 VO1 Output Voltage 1 This pin is connected to the control MOSFET switch source, which connects to a load. Internally, this
voltage is used for SS control.
3 SS1 Soft-Start Duration Set A capacitor from this pin to ground sets the output soft-start ramp slope. This capacitor is charged by
Input
the internal 10µA current source setting the soft-start ramp. The output voltage ramp tracks the SS
ramp by controlled enhancement of FET gate. Once ramp-up is completed, the capacitor continues
to charge to the CPVDD voltage rail. If common capacitor is used (by tying SS1, SS2 together and
the capacitor to GND from the connection) then both the outputs track each other as they ramp up.
4
GT1 Gate Drive Output
Direct connection to the gate of the external N-Channel MOSFET. At turn-on the Gate will charge to
4 X Vbias or 10V(max) from the 24µA source.
5 FLT1 Fault Output
This is an open drain output. It asserts (pulls low) once the current regulation duration (determined
by the CTx timeout cap) has expired. This output is valid for Vbias>1V.
6 PG1 Power Good Output This is an active low, open drain output. When asserted (logic zero), it indicates that the voltage on
UV1 pin is more than 643mV (633mV + 10mV hysteresis). This output is valid at VBIAS >1V.
7 CT1 Timer Capacitor
A capacitor from this pin to ground controls the current regulation duration from the onset of current
regulation to channel shutdown (current limit time-out). Once the voltage on CTx cap reaches
VCT_Vth the GATE output is pulled down and the FLT is asserted.
The duration of current limit time-out = (CTIM*1.178)/10µA
When the OC comparator trips AND the RTR/LTCH pin is pulled low, the IC’s faulty channel remains
shut down for 64 cycles (each cycle length is equal to the current limit time-out duration).
8 RTR/ Retry Or Latch Input This input dictates the IC behavior (for either channel) under OC condition. If it is pulled high (or left
LTCH
floating), the IC will shut down upon OC time-out. If it is pulled low, the IC will go into retry mode after
an interval determined by the capacitor on CTx pin. The faulting channel will remain shut down for
64 cycles and will try to come out of it on the 65th cycle. Each cycle length is determined by the
formula shown in CT pin description.
9 GND Chip Gnd
This pin is also internally shorted to the metal tab at the bottom of the IC.
10 PGND
Charge pump ground. Both GND and PGND must be tied together externally.
3 FN9186.3
January 3, 2006


3Pages


ISL6173 電子部品, 半導体
ISL6173
Electrical Specifications
PARAMETER
VDD = 2.5V to +3.3V, VS = 1V ,TA = TJ = 0°C - 85°C, Unless Otherwise Specified. (Continued)
SYMBOL
TEST CONDITIONS
MIN TYP MAX
GATE Voltage
VGATE
Bias = 2.5V (see graph on page 7)
7.5
9.0
2.1 < Bias < 2.5
(see graph on page 7)
8
BIAS
Supply Current
POR Rising Threshold
IBIAS
VIN_POR_L2H
VBIAS = 3.3V
9 17
2.12
POR Falling Threshold
VIN_POR_H2L
2.10
POR Threshold Hysteresis
VIN_POR_HYS
5
I/O
Undervoltage Comparator Falling
Threshold
VUV_VTHF
620 635 650
Undervoltage Comparator Hysteresis
EN Rising Threshold
EN Falling Threshold
EN Hysteresis
PG Pull-Down Voltage
FLT Pull-Down Voltage (Note 3)
Soft-Start Charging Current
VUV_HYST
PWR_Vth_R
PWR_Vth_F
PWR_HYST
VOL_PG
VOL_FLT
IQ_SS
VBIAS = 2.5V
VBIAS = 2.5V
VBIAS = 2.5V
IPG = 8mA
IFLT = 8mA
VSS = 1V
7 16 25
1.55 1.95 2.19
0.97 1.10 1.30
600 850 1100
0.047
0.4
0.047
0.4
10
CHARGE PUMP
CPVDD
CPVDD
V_CPVDD
V_CPVDD
VBIAS = 3.3V
VBIAS = 3.3V
T = 25°C
External User Load = 6mA
4.9 5.2 5.5
5.0
UNIT
V
V
mA
V
V
mV
mV
mV
V
V
mV
V
V
µA
V
V
6 FN9186.3
January 3, 2006

6 Page



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共有リンク

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部品番号部品説明メーカ
ISL6172

Dual Low Voltage Hot Swap Controller

Intersil Corporation
Intersil Corporation
ISL6172DRZA

Dual Low Voltage Hot Swap Controller

Intersil Corporation
Intersil Corporation
ISL6172DRZA-T

Dual Low Voltage Hot Swap Controller

Intersil Corporation
Intersil Corporation
ISL6173

Dual Low Voltage Hot Swap Controller

Intersil Corporation
Intersil Corporation


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