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PDF ISL97522 Data sheet ( Hoja de datos )
| Número de pieza | ISL97522 | |
| Descripción | 4-Channel TFT-LCD Supply | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
December 13, 2006
ISL97522
FN7445.0
4-Channel TFT-LCD Supply
The ISL97522 represents a 4-channel supply control IC for
use in large panel TFT-LCD displays. Supporting inputs from
4.5V to 13V, the ISL97522 includes a boost controller to
achieve the required AVDD output voltage. Both VON and
VOFF are generated using off-chip charge-pumps which are
then post regulated using on-board LDO controllers.
The logic supply is generated using an internal non-
synchronous buck controller. This controller runs at 180° out
of phase with the AVDD supply to minimize input noise.
The AVDD, VOFF, and VON outputs are automatically
sequenced as AVDD, VOFF, and VON. By using an optional
external series transistor with AVDD (Q1), the start-up
sequence can be adjusted to VOFF, AVDD and then VON. A
VON slicing circuit is also included to reduce LCD flicker.
The ISL97522 also incorporates a fault protection circuit that
can disable the IC and turn off all outputs when an output
short is detected. (Note that to protect AVDD a single
external transistor is required).
Ordering Information
www.DataSheet4U.comPART NUMBER
PART
TAPE & PACKAGE PKG.
(Note)
MARKING REEL (Pb-Free) DWG. #
ISL97522IRZ-TK ISL 97522IRZ 13” 38 Ld QFN L38.5x7B
(1k pcs)
ISL97522IRZ-T ISL 97522IRZ 13” 38 Ld QFN L38.5x7B
(4k pcs)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• 4.5V to 13V input
• Boost controller for AVDD
• Regulated LDOs for VOFF and VON
• Buck controller for logic output
• VON slicing circuit
• Fully fault-protected
• Programmable sequence
• 1MHz switching frequency
• 38 Ld QFN package
• Pb-free plus anneal available (RoHS compliant)
Applications
• LCD-TVs (up to 50”+)
• LCD monitors (15”+)
• Industrial/medical LCD displays
Pinout
ISL97522
(38 LD QFN)
TOP VIEW
DRVN 1
DELB 2
FBN 3
VCC1 4
FBB 5
ISADJB 6
ILADJB 7
CINTB 8
DRVB 9
PGNDB 10
VHIB 11
NC 12
THERMAL
PAD
31 FBP
30 VREF
29 ACGND
28 NC
27 DRVP
26 NC
25 VDCP
24 VDC
23 ISADJL
22 CINTL
21 ILADJL
20 PBL
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
Typical Performance Curves
ISL97522
100
90
80
70
60
50
40
30
20
10
0
0
VIN = 5V, AVDD = 12V
VIN = 12V, AVDD = 17V
500 1000 1500 2000
IAVDD (mA)
FIGURE 1. BOOST AVDD EFFICIENCY
2500
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
0
VIN = 12V, AVDD = 17V
VIN = 5V, AVDD = 12V
500 1000 1500 2000 2500
IAVDD (mA)
FIGURE 2. BOOST AVDD LOAD REGULATION
17.04
17.02
17
16.98
VO = 17V
16.96
16.94
16.92
16.9
16.88
0 2 4 6 8 10 12 14 16
VIN (V)
FIGURE 3. BOOST AVDD LINE REGULATION
100
90
80
70
60
50
40
30
20
10
0
0
VIN = 5V, VLOGIC = 3V
VIN = 12V, VLOGIC = 3V
500 1000 1500 2000 2500
ILOGIC (mA)
FIGURE 4. BUCK VLOGIC EFFICIENCY
0
-0.2
VIN = 5V, VLOGIC = 3V
-0.4
-0.6
-0.8 VIN = 12V, VLOGIC = 3V
-1
-1.2
0
500 1000 1500 2000 2500
ILOGIC (mA)
FIGURE 5. BUCK VLOGIC LOAD REGULATION
5
19.75
19.74
19.73
19.72
19.71
19.7
19.69
19.68
19.67
19.66
0
VON = 20V
5 10 15 20 25
IVON (mA)
FIGURE 6. VON LOAD REGULATION
FN7445.0
December 13, 2006
5 Page 
ISL97522
FBB
CINTB
VREF REFERENCE
GENERATOR
OSCILLATOR
SLOPE
COMPENSATION
OSC
PWM
Σ LOGIC
CONTROLLER
GM
AMPLIFIER
BUFFER
VIN
DRVB
ISADJ
ISIN
UVLO
COMPARATOR
SHUTDOWN
& STARTUP
CONTROL
CURRENT
AMPLIFIER
CURRENT LIMIT
COMPARATOR
CURRENT
LIMIT REF
GENERATOR
ILADJ
VBOOST
FIGURE 15. FUNCTION DIAGRAM OF THE BOOST CONTROLLER
The internal current limit circuitry is shown in Figure 16. The
circuit senses the voltage across the RDS(ON) when the
MOSFET is on; then compare it to the internal voltage
reference to realize the current limit. The internal voltage
reference is generated by a 10mA current and any additional
current set at ILADJB pin flowing through an 8kΩ resistor.
The voltage reference is based on the following equation:
VTHRESHOLD
=
⎛
⎜
⎝
V-----I--L---A----D----J---B--
R1
+
10
μ
⎞
A⎟
⎠
× 8K
(EQ. 3)
Where VILADJB is the voltage at pin ILADJ.
Where VISAD is the voltage at pin ISAD.
VISAD = VREF – VBE – 1K × ISAD
ISAD
=
V-----I--S---A----D---
R1
(EQ. 4)
Where VBE ≈ 0.7V
The external resistor R1 should be chosen in the order of
100K to generate µA of current.
VDD
10µA
VREF
1k
R1 ILADJB
-
+
8k
ISINB
LX
LOGIC
CONTROLLER
DRVB
FIGURE 16. CURRENT LIMIT BLOCK DIAGRAM
Hence the maximum output current is determined by the
following equation:
IOMAX
=
⎛
⎜
⎝
V-----T---H-----R----E----S----H----O----L----D--
RDSON
– -Δ--2--I--L-⎠⎞
× V-----I--N--
VO
(EQ. 5)
Where ΔIL is the peak to peak inductor ripple current, and is
set by:
ΔIL
=
-V----I--N--
L
×
-D---
fS
(EQ. 6)
11 FN7445.0
December 13, 2006
11 Page | ||
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| PDF Descargar | [ Datasheet ISL97522.PDF ] | |
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