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PDF ISL95810 Data sheet ( Hoja de datos )
| Número de pieza | ISL95810 | |
| Descripción | Single Digitally Controlled Potentiometer | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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ISL95810
®
Single Digitally Controlled Potentiometer (XDCP™)
Data Sheet
September 19, 2006
FN8090.2
Low Noise, Low Power I2C Bus, 256 Taps
The ISL95810 integrates a digitally controlled potentiometer
(XDCP) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the I2C
bus interface. The potentiometer has an associated volatile
Wiper Register (WR) and a non-volatile Initial Value Register
(IVR), that can be directly written to and read by the user.
The content of the WR controls the position of the wiper. At
power-up the device recalls the contents of the DCP’s IVR to
the WR.
The DCP can be used as three-terminal potentiometer or as
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.
Features
• 256 resistor taps - 0.4% resolution
• I2C serial interface
• Wiper resistance: 70Ω typical @ 3.3V
• Non-volatile storage of wiper position
• Standby current 5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ, 10kΩ total resistance
• High reliability
- Endurance: 200,000 data changes per bit per register
- Register data retention: 50 years @ T ≤ +75°C
• 8 Ld MSOP and 8 Ld TDFN packaging
• Pb-free plus anneal available (RoHS compliant)
Ordering Information
Pinouts
PART RTOTAL
TEMP
PART NUMBER MARKING (kΩ) RANGE (°C) PACKAGE
ISL95810WIU8*
www.DataSheet4U.comISL95810WIU8Z
(Note)
AIU
APN
10 -40 to +85 8 Ld MSOP
-40 to +85 8 Ld MSOP
(Pb-free)
ISL95810WIRT8Z*
(Note)
APO
-40 to +85 8 Ld 3 x 3 TDFN
(Pb-free)
ISL95810UIU8*
AIT 50 -40 to +85 8 Ld MSOP
ISL95810UIU8Z*
(Note)
AOK
-40 to +85 8 Ld MSOP
(Pb-free)
ISL95810UIRT8
AIT
-40 to +85 8 Ld 3 x 3 TDFN
ISL95810UIRT8Z*
(Note)
APP
-40 to +85 8 Ld 3 x 3 TDFN
(Pb-free)
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
WP
SCL
SDA
GND
ISL95810
(8 LD MSOP)
TOP VIEW
18
27
36
45
VCC
RH
RL
RW
ISL95810
(8 LD TDFN)
TOP VIEW
WP 1
SCL 2
SDA 3
GND 4
8 VCC
7 RH
6 RL
5 RW
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Corporation. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL95810
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (Note 1)
Rpu (Note 13)
SDA and SCL Bus Pull-Up Resistor Maximum is determined by tR and tF.
Off-Chip
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
1
tWP (Notes 13, 14) Non-Volatile Write Cycle Time
tSU:WP
WP Setup Time
tHD:WP
WP Hold Time
Before START condition
After STOP condition
12
600
600
MAX
20
UNITS
kΩ
ms
ns
ns
SDA vs SCL Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
SDA
(INPUT TIMING)
tHD:STA
tSU:DAT
SDA
(OUTPUT TIMING)
WP Pin Timing
SCL
START
CLK 1
tHD:DAT
tAA tDH
tSU:STO
tBUF
STOP
tHD:STO
tHD:STO:NV
SDA IN
tSU:WP
tHD:WP
WP
NOTES:
1. Typical values are for TA = +25°C and 3.3V supply voltage.
2. LSB: [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = V(RW)0/LSB.
4. FS error = [V(RW)255 – VCC]/LSB.
5. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
6. INL = [V(RW)i – (i • LSB – V(RW)0)]/LSB for i = 1 to 255.
7.
TCV
=
-------M-----a----x----(--V----(---R-----W------)--i--)---–-----M-----i--n----(--V-----(--R-----W------)--i--)------ × ----1----0---6-----
[Max(V(RW)i) + Min(V(RW)i)] ⁄ 2 125°C
for i = 16 to 240 decimal, T = -40°C to +85°C. Max( ) is the maximum value of the wiper
voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
8. MI = |R255 – R0|/255. R255 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.
Roffset = R0/MI, when measuring between RW and RL.
9. Roffset = R255/MI, when measuring between RW and RH.
10. RDNL = (Ri – Ri-1)/MI, for i = 32 to 255.
11. RINL = [Ri – (MI • i) – R0]/MI, for i = 32 to 255.
12.
TCR
=
----[---M-----a----x----(--R-----i--)---–-----M-----i--n----(--R-----i--)--]---- × ----1----0---6-----
[Max(Ri) + Min(Ri)] ⁄ 2 125°C
for i = 32 to 255, T = -40°C to +85°C. Max( ) is the maximum value of the resistance and Min ( ) is the
minimum value of the resistance over the temperature range.
13. This parameter is not 100% tested.
14.
tWC is the minimum cycle time to be
valid STOP condition at the end of a
allowed for any non-volatile Write by the
Write sequence of a I2C serial interface
user,
Write
unless Acknowledge
operation, to the end
Polling is used. It is the time from a
of the self-timed internal non-volatile
write cycle.
15. VIL = 0V, VIH = VCC
5 FN8090.2
September 19, 2006
5 Page 
ISL95810
received. If the Address Byte is 0 or 2, the Data Byte is
transferred to the Wiper Register (WR) or to the Access
Control Register respectively, at the falling edge of the SCL
pulse that loads the last bit (LSB) of the Data Byte. If the
Address Byte is 0, and the Access Control Register is all
zeros (default), then the STOP condition initiates the internal
write cycle to non-volatile memory.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL95810 responds with an ACK. Then the ISL95810
then transmits the Data Byte. The master then terminates
the read operation (issuing a STOP condition) following the
last bit of the Data Byte (See Figure 18).
The byte at address 02h determines if the Data Bytes being
read are from volatile or non-volatile memory (See “Memory
Description” on page 8.)
11 FN8090.2
September 19, 2006
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ISL95810.PDF ] | |
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