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PDF ISL97651 Data sheet ( Hoja de datos )

Número de pieza ISL97651
Descripción 4-Channel Integrated LCD Supply
Fabricantes Intersil Corporation 
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®
Data Sheet
March 15, 2007
ISL97651
FN7493.2
4-Channel Integrated LCD Supply
The ISL97651 represents a high power, integrated LCD
supply IC targeted at large panel LCD displays. The
ISL97651 integrates a high power, 4.4A boost converter for
AVDD generation, an integrated VON charge pump, a VOFF
charge pump driver, VON slicing circuitry and a buck
regulator with 2A switch for logic generation.
The ISL97651 have been designed for ease of layout and
low BOM cost. Supply sequencing is integrated for both
AVDD -> VOFF -> VON and AVDD/VOFF -> VON sequences.
The TFT power sequence uses a separate enable to the
logic buck regulator for maximum flexibility.
Peak efficiencies are 90% for boost and 92% for buck while
operating from a 4V to 5.5V input supply. The current mode
buck offers superior line and load regulation. Available in the
36 Ld QFN package, the ISL97651 is specified for ambient
operation over the -40°C to +105°C temperature range.
Pinout
ISL97651
(36 LD TQFN)
TOP VIEW
VIN1 1
LX1 2
LX2 3
CB 4
LXL 5
VSUP 6
FBL 7
CM2 8
CTL 9
THERMAL
PAD
27 AGND
26 PGND1
25 PGND2
24 VINL
23 NOUT
22 PGND3
21 FBN
20 VREF
19 FBP
Features
• 4V to 5.5V input supply
• AVDD boost up to 20V, with integrated 4.4A FET
• Integrated VON charge pump, up to 34V out
• VOFF charge pump driver, down to -18V
• VLOGIC buck down to 1.2V, with integrated 2A FET
• Automatic start-up sequencing
- AVDD -> VOFF -> VON or AVDD/VOFF -> VON
- Independent logic enable
• VON slicing
• Thermally enhanced thin QFN package (6mmx6mm)
• Pb-free plus anneal available (RoHS compliant)
Applications
• LCD monitors (15”+)
• LCD-TVs (40”+)
• Notebook displays (up to 16”)
• Industrial/medical LCD displays
Ordering Information
PART NUMBER
(Note)
PART
TAPE & PACKAGE PKG.
MARKING REEL (Pb-Free) DWG. #
ISL97651ARTZ-T ISL976 51ARTZ 13” 36 Ld 6x6 L36.6x6
(4k pcs) TQFN
ISL97651ARTZ-TK ISL976 51ARTZ 13” 36 Ld 6x6 L36.6x6
(1k pcs) TQFN
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




ISL97651 pdf
ISL97651
Electrical Specifications VIN = 5V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over-temperature from -40°C to +105°C, unless
otherwise stated. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN TYP MAX UNIT
FAULT DETECTION THRESHOLDS
T_off
Thermal Shut-Down (latched and
reset by power cycle or EN cycle)
Temperature rising
150 °C
Vth_AVDD(FBB) AVDD Boost Short Detection
V(FBB) falling less than
Vth_VLOGIC(FBL) VLOGIC Buck Short Detection
V(FBL) falling less than
Vth_POUT(FBP) POUT Charge Pump Short Detection V(FBP) falling less than
Vth_NOUT(FBN) NOUT Charge Pump Short Detection V(FBN) rising more than
tFD Fault Delay Time to Chip Turns Off CDEL = 220nF
START-UP SEQUENCING
0.9 V
0.9 V
0.9 V
0.4 V
52 ms
tSTART-UP
IDELB_ON
Enable to AVDD Start Time
DELB Pull-Down Current or
Resistance when Enabled by the
Start-Up Sequence
CDEL = 220nF
VDELB > 0.9V
VDELB < 0.9V
36
1000
80
50
1326
70
1750
ms
µA
Ω
IDELB_OFF
DELB Pull-Down Current or
Resistance when Disabled
VDELB < 20V
500 nA
tVOFF
tVON
tVON-SLICE
AVDD to VOFF
VOFF to VON Delay
VON to VON-SLICE Delay
CDEL = 220nF
CDEL = 220nF
CDEL = 220nF
9 ms
20 ms
17 ms
Typical Performance Curves
100
80
VIN = 5V, AVDD = 15V
60
40
20
0
0 200 400 600 800
IOUT (mA)
FIGURE 1. AVDD EFFICIENCY vs IOUT
1000
0.10
0.05
0
VIN = 5V, AVDD = 15V
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
0
200 400 600 800 1000 1200
IOUT (mA)
FIGURE 2. AVDD LOAD REGULATION vs IOUT
5 FN7493.2
March 15, 2007

5 Page





ISL97651 arduino
ISL97651
Applications Information
The ISL97651 provides a complete power solution for TFT
LCD applications. The system consists of one boost
converter to generate the AVDD voltage for column drivers,
one buck converter to provide voltage to logic circuit in the
LCD panel, one integrated VON charge pump and one VOFF
linear-regulator controller to provide the voltage to row
drivers. This part also integrates VON-slice circuit which can
help to optimize the picture quality. With the high output
current capability, this part is ideal for big screen LCD TV
and monitor panel application.
The integrated boost converter and buck converter operate
at 1.2MHz which can allow the use of multilayer ceramic
capacitors and low profile inductor which result in low cost,
compact and reliable system. The logic output voltage is
independently enabled to give flexibility to the system
designers.
Boost Converter
The boost converter is a current mode PWM converter
operating at a fixed frequency of 1.2MHz. It can operate in
both discontinuous conduction mode (DCM) at light load and
continuous mode (CCM). In continuous current mode,
current flows continuously in the inductor during the entire
switching cycle in steady state operation. The voltage
conversion ratio in continuous current mode is given by
Equation 1:
V-----B----O----O-----S----T-
VIN
=
------1-------
1D
(EQ. 1)
Where D is the duty cycle of the switching MOSFET
Figure 11 shows the functional block diagram of the boost
regulator. It uses a summing amplifier architecture consisting
of gm stages for voltage feedback, current feedback and
slope compensation. A comparator looks at the peak
inductor current cycle by cycle and terminates the PWM
cycle if the current limit is reached.
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 60kΩ is recommended.
The boost converter output voltage is determined by
Equation 2:
VBOOST
=
(---R-----3----+-----R----5----)
R5
×
VREF
(EQ. 2)
The current through the MOSFET is limited to a minimum of
4.4APEAK (maximum values can be up to 6.3APEAK.
This restricts the maximum output current (average) based
on Equation 3:
IOMAX
=
IL
M
T
-Δ--2--I--L-⎠⎞
×
V-----I--N--
VO
(EQ. 3)
Where ΔIL is peak to peak inductor ripple current, and is set
by Equation 4:
ΔIL
=
-V----I--N--
L
×
-D---
fS
(EQ. 4)
where fS is the switching frequency (1.2MHz).
Table 1 gives typical values (margins are considered 10%,
3%, 20%, 10% and 15% on VIN, VO, L, fS and IOMAX:
TABLE 1. MAXIMUM OUTPUT CURRENT CALCULATION
VIN (V)
4
VO (V)
9
L (µH)
6.8
FS (MHz)
1.2
IOMAX
(mA)
1661
4 12 6.8 1.2 1173
4 15 6.8 1.2 879
5 9 6.8 1.2 2077
5 12 6.8 1.2 1466
5 15 6.8 1.2 1099
Boost Converter Input Capacitor
An input capacitor is used to suppress the voltage ripple
injected into the boost converter. A ceramic capacitor with
capacitance larger than 10µF is recommended. The voltage
rating of input capacitor should be larger than the maximum
input voltage. Examples of recommended capacitors are
given in Table 2 below.
TABLE 2. BOOST CONVERTER INPUT CAPACITOR
RECOMMENDATION
CAPACITOR SIZE VENDOR
PART NUMBER
10µF/16V
1206
TDK C3216X7R1C106M
10µF/10V
0805 Murata GRM21BR61A106K
22µF/10V
1210 Murata GRB32ER61A226K
Boost Inductor
The boost inductor is a critical component which influences
the output voltage ripple, transient response, and efficiency.
Values of 3.3µH to 10µH are to match the internal slope
compensation. The inductor must be able to handle without
saturating the following average and peak current:
ILAVG
=
----I--O-------
1D
ILPK
=
IL
A
VG
+
-Δ----I--L-
2
(EQ. 5)
11 FN7493.2
March 15, 2007

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