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PDF ISL9208 Data sheet ( Hoja de datos )
| Número de pieza | ISL9208 | |
| Descripción | Multi-Cell Li-ion Battery Pack OCP/Analog Front End | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
February 16, 2007
ISL9208
FN6446.0
Multi-Cell Li-ion Battery Pack OCP/Analog
Front End
The ISL9208 is an overcurrent protection device and analog
front end for a microcontroller in a multi-cell Li-ion battery
pack. The ISL9208 supports battery pack configurations
consisting of 5 cells to 7 cells in series and 1 or more cells in
parallel. The ISL9208 provides integral overcurrent
protection circuitry, short circuit protection, an internal 3.3V
voltage regulator, internal cell balancing switches, cell
voltage monitor level shifters, and drive circuitry for external
FET devices for control of pack charge and discharge.
Selectable overcurrent and short circuit thresholds reside in
internal RAM registers. An external microcontroller sets the
thresholds by setting register values through an I2C serial
interface. Internal registers also contain the detection delays
for overcurrent and short circuit conditions.
Using an internal analog multiplexer the ISL9208 provides
monitoring of each cell voltage plus internal and external
temperature by a separate microcontroller with an A/D
converter. Software on this microcontroller implements all
battery pack control functionality, except for overcurrent and
short circuit shutdown.
Ordering Information
PART NUMBER
PART
(Note)
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL9208IRZ* ISL9208 IRZ 32 Ld 5x5 QFN L32.5x5B
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Software selectable overcurrent protection levels and
variable protect detection times
- 4 discharge overcurrent thresholds
- 4 short circuit thresholds
- 4 charge overcurrent thresholds
- 8 overcurrent delay times (Charge)
- 8 overcurrent delay times (Discharge)
- 2 short circuit delay times (Discharge)
• Automatic FET turn-off and cell balance disable on
reaching external (battery) or internal (IC) temperature
limit.
• Automatic over-ride of cell balance on reaching internal
(IC) temperature limit.
• Fast short circuit pack shutdown
• Can use current sense resistor, FET rDS(ON), or Sense
FET for overcurrent detection.
• Four battery backed software controlled flags.
• Allows three different FET controls:
- Back-to-back N-Channel FETs for charge and discharge
control
- Single N-Channel discharge FET.
- Single N-Channel FET for discharge, with separate,
optional (smaller) back-to-back N-channel FETs for
charge.
• Integrated Charge/Discharge FET Drive Circuitry with
200µA (typ) turn-on current and 150mA (typ) Discharge
FET turn-off current.
• 10% Accurate 3.3V voltage regulator (minimum 25mA out
with external NPN transistor having current gain of 70).
• Monitored cell voltage output stable in 100µs.
• Internal Cell balancing FETs handle up to 200mA of
balancing current for each cell (with the number of cells
being balanced limited by the maximum package power
dissipation of 400mW).
• Simple I2C host interface
• Sleep operation with programmable negative edge or
positive edge wake up.
• <10µA Sleep Mode
• Pb-free plus anneal available (RoHS compliant)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL9208
Absolute Maximum Ratings
Power Supply Voltage, VCC . . . . . . . . . .VSS - 0.5V to VSS + 36.0V
Cell voltage, VCELL
VCELLN - (VCELLN-1), VCELL1-VSS . . . . . . . . . . . . . -0.5V to 5V
Terminal Voltage, VTERM1
(SCL, SDA, CSENSE, DSENSE, TEMPI, RGO, AO, TEMP3V)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS-0.5 to VRGO + 0.5V
Terminal Voltage, VTERM2 (CFET, VMON) . . . . VSS - 22.0V to VCC
Terminal Voltage, VTERM3 (WKUP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 0.5V to VCC(VCC < 27V)
Terminal Voltage, VTERM4 (RGC) . . . . . . . . . . . . . VSS - 0.5V to 5V
Terminal Voltage, VTERM5, (all other pins)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 0.5V to VCC + 0.5V
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 5V to 10V
Operating Voltage:
VCC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 to 30.1V
VCELL1-VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 4.3V
VCELLN-(VCELLN-1). . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 4.3V
Thermal Information
Thermal Resistance (Typical, Note 1, 2) θJA (°C/W) θJC (°C/W)
32 Ld QFN . . . . . . . . . . . . . . . . . . . . . .
32
2
Continuous Package Power Dissipation . . . . . . . . . . . . . . . . .400mW
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125°C
Lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . +300°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Operating Specifications Over the recommended operating conditions unless otherwise specified
PARAMETER
SYMBOL
TEST CONDITION
MIN
Operating Voltage
Power Up Condition 1
Power Up Condition 2 Threshold
VCC
VPORVCC VCC voltage (Note 3)
VPOR123 VCELL1 - VSS and VCELL2 - VCELL1 and
VCELL3 - VCELL2 (rising)
(Note 3)
9.2
1.1
Power Up Condition 2 Hysteresis
VPORhys VCELL1 - VSS and VCELL2 - VCELL1 and
VCELL3 - VCELL2 (falling)
(Note 3)
3.3V Regulated Voltage
3.3VDC Voltage Regulator Control
Current Limit
VRGO
IRGC
0µA < IRGC < 350µA
(Control current at output of RGC.
Recommend NPN with gain of 70+)
3.0
0.35
VCC Supply Current
RGO Supply Current
VCC Supply Current
RGO Supply Current
IVCC1
IRGO1
IVCC2
IRGO2
Power up defaults, WKUP pin = 0V.
LDMONEN bit = 1, VMON floating,
CFET = 1, DFET=1, WKPOL bit = 1,
VWKUP = 10V, [AO3:AO0] bits = 03H.
VCC Supply Current
RGO Supply Current
VCELL Input Current - VCELL1
VCELL Input Current - VCELLN
IVCC3 Default register settings, except
SLEEP bit = 1. WKUP pin = VCELL1
IRGO3
IVCELL1 AO3:AO0 bits = 0000H
IVCELLN AO3:AO0 bits = 0000H
TYP
4
1.7
70
3.3
0.50
400
300
500
450
MAX
30.1
9.2
2.3
UNIT
V
V
V
mV
3.6 V
mA
510 µA
410 µA
700 µA
650 µA
10 µA
1 µA
14 µA
10 µA
5 FN6446.0
February 16, 2007
5 Page 
ISL9208
Automatic Temperature Scan
AUTO TEMP CONTROL
(INTERNAL ACTIVATION)
MONITOR TIME = 4ms
TEMP3V PIN
EXTERNAL
TEMPERATURE
3.3V
508ms
HIGH IMPEDANCE
OVER-TEMPERATURE
THRESHOLD
TMP3V/13
DELAY TIME = 1ms
XOT BIT
DELAY TIME = 1ms
MONITOR TEMP DURING THIS
TIME PERIOD
FET SHUTDOWN AND CELL BALANCE TURN OFF
(IF ENABLED)
Discharge Overcurrent/Short Circuit Monitor (assumes DENOCD and DENSCD bits are ‘0’)
VSC
VOCD
VDSENSE
DOC BIT
DSC BIT
TEMP3V
OUTPUT
VCELL3
DFET
OUTPUT
tSCD
‘0’
‘0’
tOCD
3.3V
tSCD
‘1’
‘1’
REGISTER 1 READ
REGISTER 1 READ
UC TURNS ON DFET
11 FN6446.0
February 16, 2007
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet ISL9208.PDF ] | |
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