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PDF ISL8724 Data sheet ( Hoja de datos )
| Número de pieza | ISL8724 | |
| Descripción | (ISL8723 / ISL8724) Power Sequencing Controllers | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
ISL8723, ISL8724
December 21, 2006
FN6413.0
Power Sequencing Controllers
The Intersil ISL8723 and ISL8724 are 4 channel sequencers
controlling the on and off sequence of voltages with under
voltage supply fault protection and a “sequence completed”
signal (RESET#). For larger systems, more than 4 voltages
can be sequenced by a simple connection of multiple IC's.
These sequencers use an integrated charge pump to drive 4
external low-cost N-channel MOSFET switch gates above
the IC bias voltage by 5.3V. These IC's can be biased from
and control any supply from 2.5V to 5V and additionally
monitor any voltage above 0.7V. Individual product
descriptions are below.
The four channel ISL8723 (ENABLE input), ISL8724
(ENABLE# input) offer the designer 4 voltage control when it
is required that all four rails are in minimal compliance prior
to turn on and that compliance must be maintained during
operation. The ISL8723 has a low power standby mode
when it is disabled suitable for battery powered applications.
External resistors provide flexible voltage threshold
programming of monitored voltages. Delay and sequencing
timing are programmable by external capacitors for both
ramp up and ramp down.
Ordering Information
PART NUMBER
TEMP.
PART RANGE
MARKING (°C)
PKG.
PACKAGE DWG. #
ISL8723IRZ (Note) 8723IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4
ISL8724IRZ (Note) 8724IRZ
(Pb-free)
L24.4x4
ISL8723IRZ-T (Note) 8723IRZ
ISL8724IRZ-T (Note) 8724IRZ
-40 to +85 24 Ld 4x4 QFN L24.4x4
(Pb-free)
L24.4x4
Tape & Reel
ISL8723EVAL1
Evaluation Platform
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Enables arbitrary turn-on and turn-off sequencing of up to
four power supplies (0.7V to 5V)
• Operates from 2.5V to 5V supply voltage
• Supplies VDD +5.3V of charge pumped gate drive
• Adjustable voltage slew rate for each rail
• Multiple sequencers can be easily daisy-chained to
sequence an infinite number of independent voltages
• Glitch immunity
• Under voltage lockout for each monitored supply voltage
• 30µA Sleep State (ISL8723)
• Active high (ISL8723) or low (ISL8724) ENABLE# input
• Pb-free plus anneal available (RoHS compliant) QFN
Package
Applications
• Graphics cards
• FPGA/ASIC/microprocessor/PowerPC supply sequencing
• Network Routers
• Telecommunications Systems
Pinout
ISL8723, ISL8724
(24 LD QFN)
TOP VIEW
24 23 22 21 20 19
ENABLE/
ENABLE# 1
18 DLY_OFF_A
GATE_A 2
17 UVLO_C
DLY_OFF_C 3
DLY_OFF_D 4
4mmx4mm
16 DLY_ON_C
15 DLY_ON_D
GATE_B 5
14 UVLO_D
GATE_C 6
13 DLY_OFF_B
7 8 9 10 11 12
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL8723, ISL8724
Electrical Specifications
PARAMETER
VDD = 3.3V to +5V, TA = TJ = -40°C to +85°C, Unless Otherwise Specified. (Continued)
SYMBOL
TEST CONDITIONS
MIN TYP MAX
SYSRST# Output Capacitance
Cout_srst
- 10 -
SYSRST# Low to GATE Turn-off
SYSRST# High to GATE Turn-on
GATE
TdelSYS_G_1 GATE = 80% of VDD+5V
TdelSYS_G_2 GATE = 50% of VDD+5V
- 40 -
- 0.4 -
GATE Turn-On Current
GATE Turn-Off Current
GATE Current Range
GATE Pull-Down High Current
GATE High Voltage
GATE Low Voltage
BIAS
IGATEon
IGATEoff_l
IGATE_range
IGATEoff_h
VGATEh5
VGATEl
GATE = 0V
GATE = VDD, Disabled
Within IC IGATE max-min
GATE = VDD, UVLO = 0V
VDD = 5V
Gate Low Voltage, VDD = 1V
8.3 10.2
-12.5
-10.2
- 0.6
- 75
VDD+5.3V VDD+5.6V
- 0.01
12.5
-8.3
3
-
-
0.1
IC Supply Current
ISL8723 Stand By IC Supply Current
VDD Power On Reset
IVDD_5V VDD = 5V, Enabled and static - 0.27 0.31
IVDD_sb
VDD = 5V, ENABLE = 0V
- 30 40
VDD_POR VDD rising
- 2.2 2.41
UNIT
pF
ns
ms
μA
μA
μA
mA
V
V
mA
μA
V
ISL8723, ISL8724 Descriptions and
Operation
The ISL8723 and ISL8724 sequencers are quad voltage
sequencing controllers designed for use in multiple-voltage
systems requiring power sequencing of various supply
voltages. Individual voltage rails are gated on and off by
external N-Channel MOSFETs, the gates of which are
driven by an internal charge pump to ~VDD +5.6V (VQP) in
a user programmed sequence.
With the ISL8723 the ENABLE must be asserted high and
all four voltages to be sequenced must be above their
respective user programmed Under Voltage Lock Out
(UVLO) levels before programmed output turn on
sequencing can begin. Sequencing and delay
determination is accomplished by the choice of external
cap values on the DLY_ON and DLY_OFF pins. The
SYSRST# goes high once all 4 UVLO inputs and ENABLE
are satisfied. Once all 4 UVLO inputs and ENABLE are
satisfied for 10ms, the four DLY_ON caps are
simultaneously charged with 1μA current sources to the
DLY_Vth level of 1.28V. As each DLY_ON pin reaches the
DLY_Vth level its associated GATE will then turn-on with a
10μA source current to the VQP voltage of VDD+5.6V.
Thus all four GATEs will sequentially turn on. Once at
DLY_Vth the DLY_ON pins will discharge to be ready when
next needed. After the entire turn on sequence has been
completed and all GATEs have reached the charge
pumped voltage (VQP), a 160ms delay is started to ensure
stability after which the RESET# output will be released to
go high. Subsequent to turn-on, if any input falls below its
UVLO point for longer than the glitch filter period, TFIL
(~7μs) this is considered a fault. RESET#, SYSRST# and
all GATEs are simultaneously pulled low. In this mode the
GATEs are pulled low with ~75mA. Normal shutdown mode
is entered when no UVLO is violated and the ENABLE is
deasserted. When ENABLE is deasserted, RESET# is
asserted and pulled low. Next, all four shutdown ramp caps
on the DLY_OFF pins are charged with a 1μA source and
when any ramp-cap reaches DLY_Vth, a latch is set and a
10μA current is sunk on the respective GATE pin to turn off
its external MOSFET. When the falling GATE voltage is
approximately 1.5V, the GATE is pulled down the rest of the
way at a higher current level to ensure a hard turn-off. Each
individual external FET is thus turned off removing the
voltages from the load in the programmed sequence. The
SYSRST# will pull low concurrent with the last GATE being
pulled low.
The ISL8723 and ISL8724 have the same functionality
except for the complimentary ENABLE active polarity with
the ISL8724 having an ENABLE# input. Additionally the
ISL8723 also has a low power sleep state when disabled.
Upon bias the SYSRST# and RESET# pins are held low
before bias voltage = 1V.
The SYSRST# has both an input and output function. As an
output the SYSRST# pin is useful when implementing
multiple sequencers in a design needing simultaneous
shutdown as with a kill switch across all sequencers. Once
any UVLO is unsatisfied for longer than TFIL the related
SYSRST# will pull low and pull all other SYSRST# pins low
that are on a common connection thus unconditionally
shutting down all outputs across multiple sequencers. As
an input, if it is pulled low all GATEs will be unconditionally
shut off and RESET# pulled low, see Figure 17. This pin
can also be used as a ‘no wait’ enabling input, if all inputs
(ENABLE and UVLO) are satisfied it does not wait through
5 FN6413.0
December 21, 2006
5 Page 
ISL8723, ISL8724
Typical Performance Waveforms (Continued)
SYSRST#
ENABLE
SYSRST#
RESET#
ENABLE
FIGURE 18. 4 UVLOs VALID, ENABLE HIGH to SYSRST HIGH
UVLO
FIGURE 19. ENABLE LOW to RESET# and SYSRST LOW
RESET#
SYSRST#
FIGURE 20. UVLO INVALID to RESET# and SYSRST$# LOW
11 FN6413.0
December 21, 2006
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ISL8724.PDF ] | |
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