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ISL8702A の電気的特性と機能

ISL8702AのメーカーはIntersil Corporationです、この部品の機能は「(ISL8700A - ISL8705A) Adjustable Quad Sequencer」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL8702A
部品説明 (ISL8700A - ISL8705A) Adjustable Quad Sequencer
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL8702A Datasheet, ISL8702A PDF,ピン配置, 機能
®
Data Sheet
ISL8700A, ISL8701A, ISL8702A,
ISL8703A, ISL8704A, ISL8705A
October 12, 2006
FN6381.0
Adjustable Quad Sequencer
The ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A,
ISL8705A family of ICs provide four delay adjustable
sequenced outputs while monitoring an input voltage all with
a minimum of external components.
High performance DSP, FPGA, µP and various sub-systems
require input power sequencing for proper functionality at
initial power up and the ISL870XA provides this function
while monitoring the distributed voltage for over and
undervoltage compliance.
These ICs operate over the +3.3V to +24V nominal voltage
range. All have a user adjustable time from UV and OV
voltage compliance to sequencing start via an external
capacitor when in auto start mode and adjustable time delay
to subsequent ENABLE output signal via external resistors.
Additionally, the ISL8702A, ISL8703A, ISL8704A and
ISL8705A provide I/O for sequencing on and off operation
(SEQ_EN) and for voltage window compliance reporting
(FAULT) over the +3.3V to +24V nominal voltage range.
Easily daisy chained for more than 4 sequenced signals.
Altogether, the ISL870XA provides these adjustable features
with a minimum of external BOM. See Figure 1 for typical
implementation.
Ordering Information
PART NUMBER PART
TEMP. PACKAGE PKG.
(Note 1)
MARKING RANGE (°C) (Pb-free) DWG. #
ISL8700AIBZ* ISL8700AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8701AIBZ* ISL8701AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8702AIBZ* ISL8702AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8703AIBZ* ISL8703AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8704AIBZ* ISL8704AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8705AIBZ* ISL8705AIBZ -40 to +85 14 Ld SOIC M14.15
ISL870XAEVAL1 Evaluation Platform
*Add “-T” suffix for tape and reel.
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Adjustable Delay to Subsequent Enable Signal
• Adjustable Delay to Sequence Auto Start
• Adjustable Distributed Voltage Monitoring
• Under and Overvoltage Adjustable Delay to Auto Start
Sequence
• I/O Options
ENABLE (ISL8700A, ISL8702A, ISL8704A) and
ENABLE# (ISL8701A, ISL8703A, ISL8705A)
SEQ_EN (ISL8702A, ISL8703A) and
SEQ_EN# (ISL8704A, ISL8705A)
• Voltage Compliance Fault Output
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Power Supply Sequencing
• System Timing Function
Pinout
ISL870XA
(14 LD SOIC)
TOP VIEW
ENABLE_D 1
ENABLE_C 2
ENABLE_B 3
ENABLE_A 4
OV 5
UV 6
GND 7
14 VIN
13 TD
12 TC
11 TB
10 TIME
9 SEQ_EN (NC on ISL8700A/01A)
8 FAULT (NC on ISL8700A/01A)
ISL8701A, ISL8703A, ISL8705A PINS 1-4 ARE ENABLE# FUNCTION
ISL8704A, ISL8705A PIN 9 IS SEQ_EN# FUNCTION
3.3-24V
Ru VIN ENABLE_A
SEQ_EN *
ENABLE_B
ENABLE_C
UV ENABLE_D
Rm
OV
FAULT *
GND TB TC TD TIME
Rl
EN
DC/DC
Vo1
EN
DC/DC
Vo2
EN
DC/DC
Vo3
EN
DC/DC
V04
* SEQ_EN and FAULT are not available on ISL8700A and ISL8701A
FIGURE 1. ISL870XA IMPLEMENTATION
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL8702A pdf, ピン配列
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
Pin Descriptions
PINS
8700A 8701A 8702A 8703A 8704A 8705A PIN NAME
FUNCTION DESCRIPTION
NA 1 NA 1 NA 1 ENABLE#_D Active low open drain sequenced output. Sequenced on after ENABLE#_C and first output
to sequence off for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias.
1 NA 1 NA 1 NA ENABLE_D Active high open drain sequenced output. Sequenced on after ENABLE_C and first output
to sequence off for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN < 1V.
NA 2 NA 2 NA 2 ENABLE#_C Active low open drain sequenced output. Sequenced on after ENABLE#_B and sequenced
off after ENABLE#_D for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias.
2 NA 2 NA 2 NA ENABLE_C Active high open drain sequenced output. Sequenced on after ENABLE_B and sequenced
off after ENABLE_D for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN < 1V.
NA 3 NA 3 NA 3 ENABLE#_B Active low open drain sequenced output. Sequenced on after ENABLE#_A and sequenced
off after ENABLE#_C for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias.
3 NA 3 NA 3 NA ENABLE_B Active high open drain sequenced output. Sequenced on after ENABLE_A and sequenced
off after ENABLE_C for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN < 1V.
NA 4 NA 4 NA 4 ENABLE#_A Active low open drain sequenced output. Sequenced on after CTIME period and sequenced
off after ENABLE#_B for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias.
4 NA 4 NA 4 NA ENABLE_A Active high open drain sequenced output. Sequenced on after CTIME period and
sequenced off after ENABLE_B for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN
< 1V.
555555
OV The voltage on this pin must be under its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull-ups.
666666
UV The voltage on this pin must be over its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull-ups.
777777
GND IC ground.
NA NA
NA NA
8
9
8 8 8 FAULT The VIN voltage when not within the desired UV to OV window will cause FAULT to be
released to be pulled high to a voltage equal to or less than VIN via an external resistor.
9 NA NA SEQ_EN This pin provides a sequence on signal input with a high input. Internally pulled high to ~2.4V.
NA NA NA NA 9
9 SEQ_EN# This pin provides a sequence on signal input with a low input. Internally pulled high to ~2.4V.
10 10 10 10 10 10
TIME
This pin provides a 2.6µA current output so that an adjustable VIN valid to sequencing on
and off start delay period is created with a capacitor to ground.
11 11 11 11 11 11
TB A resistor connected from this pin to ground determines the time delay from ENABLE_A
being active to ENABLE _B being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
12 12 12 12 12 12
TC A resistor connected from this pin to ground determines the time delay from ENABLE_B
being active to ENABLE _C being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
13 13 13 13 13 13
TD A resistor connected from this pin to ground determines the time delay from ENABLE_C
being active to ENABLE _D being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
14 14 14 14 14 14
VIN IC Bias Pin Nominally 3.3V to 24V
This pin requires a 1μF decoupling capacitor close to IC pin.
3 FN6381.0
October 12, 2006


3Pages


ISL8702A 電子部品, 半導体
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
An Advanced Tutorial on Setting UV and OV Levels
This section discusses in additional detail the nuances of
setting the UV and OV levels, providing more insight into the
ISL870XA than the earlier text.
The following equation set can alternatively be used to work out
ideal values for a 3 resistor divider string of Ru, Rm and Rl.
These equations assume that VREF is the center point between
VUVRvth and VUVFvth (i.e. (VUVRvth + VUVFvth)/2 = 1.17V),
Iload is the load current in the resistor string (i.e. VIN /(Ru + Rm
+ Rl)), VIN is the nominal input voltage and Vtol is the
acceptable voltage tolerance, such that the UV and OV
thresholds are centered at VIN ± Vtol. The actual acceptable
voltage window will also be affected by the hysteresis at the UV
and OV pins. This hysteresis is amplified by the resistor string
such that the hysteresis at the top of the string is:
Vhys = VUVhys x VOUT/VREF
This means that the VIN ± Vtol thresholds will exhibit
hysteresis resulting in thresholds of VIN + Vtol ± Vhys/2 and
VIN - Vtol ± Vhys/2.
There is a window between the VIN rising UV threshold and
the VIN falling OV threshold where the input level is
guaranteed not to be detected as a fault. This window exists
between the limits VIN ± (Vtol - Vhys/2). There is an
extension of this window in each direction up to
VIN ± (Vtol + Vhys/2), where the voltage may or may not be
detected as a fault, depending on the direction from which it
is approached. These two equations may be used to
determine the required value of Vtol for a given system. For
example, if VIN is 12V, Vhys = (0.1 x 12)/1.17 = 1.03V. If VIN
must remain within 12V ± 1.5V, Vtol = 1.5 - 1.03/2 = 0.99V.
This will give a window of 12 ±0.48V where the system is
guaranteed not to be in fault and a limit of 12 ±1.5V beyond
which the system is guaranteed to be in fault.
It is wise to check both these voltages, for if the latter is made to
tight, the former will cease to exist. This point comes when Vtol
< Vhys/2 and results from the fact that the acceptable window
for the OV pin no longer aligns with the acceptable window for
the UV pin. In this case, the application will have to be changed
such that UV and OV are provided separate resistor strings. In
this case, the UV and OV thresholds can be individually
controlled by adjusting the relevant divider.
The previous example will give voltage thresholds of:
with VIN rising
UVr = VIN - Vtol + Vhys/2 = 11.5V and
OVr = VIN + Vtol + Vhys/2 = 13.5V
with VIN falling
Ovf = VIN + Vtol - Vhys/2 = 12.5V and
UVf = VIN - Vtol - Vhys/2 = 10.5V.
So with a single three resistor string, the resistor values can
be calculated as:
Rl = (VREF/Iload) (1 - Vtol/VIN)
Rm = 2(VREF x Vtol)/(VIN x Iload)
Ru = 1/Iload x (VIN - VREF (1+Vtol/VIN))
For the above example, with Vtol = 0.99V, assuming a
100µA Iload at VIN = 12V:
Rl = 10.7kΩ
Rm = 1.9kΩ
Ru = 107.3kΩ
FAULT
SEQ_EN
TIME
ENABLE OUTPUTS
A B CD
DC B A
FIGURE 2. ISL8702A OPERATIONAL DIAGRAM
6 FN6381.0
October 12, 2006

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部品番号部品説明メーカ
ISL8702

Adjustable Quad Sequencer

Intersil
Intersil
ISL8702A

(ISL8700A - ISL8705A) Adjustable Quad Sequencer

Intersil Corporation
Intersil Corporation


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