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PDF ISL8121 Data sheet ( Hoja de datos )
| Número de pieza | ISL8121 | |
| Descripción | Two-Phase Buck PWM Controller | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
October 18, 2006
ISL8121
FN6352.1
3V to 20V, Two-Phase Buck PWM
Controller with Integrated 4A MOSFET
Drivers
The ISL8121 is a two-phase buck PWM controller featuring
an input voltage range of 3V to 20V and integrated MOSFET
drivers. Precision voltage regulation is provided for
point-of-load and other high-current applications that require
efficient and compact implementation. Multiphase buck
converter architecture uses interleaved timing to multiply
channel ripple frequency allowing smaller filter inductors and
reducing input and output ripple currents due to the ripple
cancellation effect. Lower ripple results in fewer input and
output capacitors. Smaller and low cost transistors can be
used resulting from the higher efficiency and reduced power
dissipation.
The ISL8121 offers an internal 0.6V reference with a system
regulation accuracy of ±0.8% (Industrial Temperature
range), an optional external reference input, and
user-adjustable switching frequency. Unity gain differential
amplifier targeted at remote voltage sensing capability
enhances the regulation. A power good signal (PGD) is
issued when the output voltage is within the regulated
window. An internal shunt regulator with optional external
connection capability extends the operational input voltage
range. For applications requiring voltage tracking or
sequencing, the ISL8121 offers a host of possibilities,
including coincidental, ratiometric, or offset tracking, as well
as sequential start-ups, user adjustable for a wide range of
applications.
Additional features include overvoltage and overcurrent
protection. Overcurrent protection can be tailored to various
applications with no need for additional parts. The ISL8121
uses cost and space-saving rDS(ON) sensing for channel
current balance, dynamic voltage positioning, and
overcurrent protection. Channel current balancing is
automatic and accurate with the integrated current-balance
control system.
Features
• Integrated Two-Phase Power Conversion
• Precision Output Voltage Regulation
- ±0.8% System Accuracy Over Temperature (Industrial)
- Differential Remote Voltage Sensing for Increased
Voltage Sensing Accuracy
• Shunt Regulator for Wide Input Power Conversion
- 5V and Higher Bias
- Up to 20V Power Down-Conversion
• Precision Channel Current Sharing
- Loss-Less rDS(ON) Current Sampling
• Integrated High Capable 4A Drivers
• 0.6V Internal Reference
• Full Spectrum Voltage Tracking
- Coincidental, Ratiometric, or Offset
• Sequential Start-up Control
• Selectable Switching Frequency up to 2MHz Per Phase
• Fast Transient Recovery Time
• Overcurrent Protection
• Overvoltage Protection
• Capable of Start-up in a Pre-Biased Load
• QFN Packages:
- QFN - Compliant to JEDEC PUB95 MO-220
- QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• General Purpose High Current DC/DC Converters
• High Current, Low Voltage FPGA/ASIC DC/DC
Converters
• Telecom System
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL8121
Absolute Maximum Ratings
Supply Voltage, VCC, PVCC . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Shunt Regulator Voltage, VVREG . . . . . . . . . . . . . . . -0.3V to +6.5V
Boot Voltage, VBOOT . . . . . . . . . . . . . PGND - 0.3V to PGND + 27V
Phase Voltage, VPHASE . . . . . . . . . . VBOOT - 7V to VBOOT + 0.3V
Upper Gate Voltage, VUG . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V
Lower Gate Voltage, VLG. . . . . . . . . . . PGND - 0.3V to VCC + 0.3V
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
Recommended Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . +4.9V to +5.5V
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
Thermal Information
Thermal Resistance
θJA (°C/W) θJC (°C/W)
QFN Package (Notes 1, 2). . . . . . . . . .
43
7
Maximum Junction Temperature (Note 3) . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to 150°C junction may trigger the shutdown of
the device even before 150°C since this number is specified as typical.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. Operation with die temperatures between +125°C and +150°C can be tolerated for short periods of time, however, in order to maximize the
operating life of the IC, it is strongly recommended that the effective continuous operating junction temperature of the die should not exceed
+125°C.
Electrical Specifications Operating Conditions: VCC = 5V, TJ = -40°C to +85°C, unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
BIAS SUPPLY AND INTERNAL OSCILLATOR
Input Bias Supply Current
Rising VCC POR (Power-On Reset) Threshold
IVCC; EN >0.7V; LG, UG open
4.30
VCC POR Hysteresis
0.46
Rising PVCC POR Threshold
3.60
Shunt Regulation
Maximum Shunt Current
Switching Frequency (per channel; Note 5)
Frequency Tolerance
Oscillator Peak-to-Peak Ramp Amplitude
Maximum Duty Cycle
CONTROL THRESHOLDS
VVCC; IVREG = 0 to 120mA
IVREG_MAX
FSW
FSW
VOSC
dMAX
4.90
120
150
-10
EN Threshold
EN Hysteresis Current
VMON Power-Good Enable Threshold
VMON Hysteresis Current
VVMON_TH
290
SOFT-START
SS Current
SS Ramp Amplitude
ISS
0.55
SS Threshold for Output Gates Turn-Off
0.40
REFERENCE AND DAC
System Accuracy (Industrial Temp. Range)
-0.8
Internal Reference
VREF
TYP
7.6
4.40
0.51
3.67
5.10
1.4
66
0.65
20
305
10
22
0.6
MAX UNITS
9
4.50
0.58
3.75
5.35
2000
10
mA
V
V
V
V
mA
kHz
%
V
%
V
µA
320 mV
µA
µA
3.60 V
V
0.8 %
V
5 FN6352.1
October 18, 2006
5 Page 
ISL8121
until the clock signals the beginning of the next switching
cycle and the PWM pulse is terminated.
CURRENT SENSING
ISL8121 senses current by sampling the voltage across the
lower MOSFET during its conduction interval. MOSFET
rDS(ON) sensing is a no-added-cost method to sense current
for load line regulation, channel current balance, module
current sharing, and overcurrent protection.
The ISEN pins are used as current inputs for each channel.
Internally, a virtual ground is created at the ISEN pins. The
RISEN resistors are used to size the current flow through the
ISEN pins, proportional to the lower MOSFETs’ rDS(ON)
voltage, during their conduction periods. The current thus
developed through the ISEN pins is internally averaged, then
the current error signals resulting from comparing the
average to the individual current signals are used for
channel current balancing.
Select the value for the RISEN resistors based on the room
temperature rDS(ON) of the lower MOSFETs and the full-load
total converter output current, IFL.
RISEN = 5-r--D-0---S--×--(-1-O--0---N-–--6-)- ⋅ -I-F-2---L-
(EQ. 5)
As this current sense path is also used for OC detection,
ensure that at maximum power train temperature rise and
maximum output current loading the OC protection is not
inadvertently tripped. OC protection current level through the
ISEN pins is listed in the Electrical Specifications table on
page 5.
CHANNEL-CURRENT BALANCE
Another benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this, the
designer avoids the complexity of driving multiple parallel
MOSFETs and the expense of using expensive heat sinks
and exotic magnetic materials.
All things being equal, in order to fully realize the thermal
advantage, it is important that each channel in a multi-phase
converter be controlled to deliver about the same current at
any load level. Intersil’s ISL8121 ensure current balance by
comparing each channel’s current to the average current
delivered by both channels and making appropriate
adjustments to each channel’s pulse width based on the
resultant error. The error signal modifies the pulse width to
correct any unbalance and force the error toward zero.
Conversely, should a channel-to-channel imbalance be
desired, such imbalance can be created by adjusting the
individual channel’s RISEN resistor. Asymmetrical layouts,
where one phase of the converter is naturally carrying more
current than the other, or where one of the two phases is
subject to a more stringent thermal environment limiting its
current-carrying capability, are instances where this
adjustment is particularly useful, helping to cancel out the
design-intrinsic thermal or current imbalances.
SOFT-START
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. As soon as the controller is fully enabled for
operation, the SS pin starts to output a small current which
charges the external capacitor, CSS, connected to this pin.
An internal reference clamp controlled by the potential at the
SS pin releases the reference to the input of the error
amplifier with a 1:1 correspondence for SS potential
exceeding 0.7V (typically). Figure 5 details a normal
soft-start start-up. The following equation helps determine
the approximate time period during which the controlled
output voltage is ramped from 0V to the desired DC-set
level.
tSS = C-----S----S---I--S⋅---V-S---R----E----F--
(EQ. 6)
VOUT (0.5V/DIV)
VintREF (0.5V/DIV)
GND>
GND>
VSS (1V/DIV)
EN (5V/DIV)
FIGURE 5. NORMAL SOFT-START WAVEFORMS FOR
ISL8121-BASED MULTI-PHASE CONVERTER
Whenever the ISL8121’s power-on reset falling threshold is
tripped, or it is disabled via the EN pin, the SS capacitor is
quickly discharged via an internal pull-down device
(represented as the 1mA, typical, current source).
As the SS pin’s positive excursion is internally clamped to
about 3.5V, insure that any external pull-up device does not
force more than 3mA into this pin.
Should OC protection be tripped while the ISL8121 is
operating in internal-reference mode and the SS pin not be
allowed to fully discharge the SS capacitor, the ISL8121
cannot continue the normal SS cycling.
11 FN6352.1
October 18, 2006
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet ISL8121.PDF ] | |
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