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PDF ISL8118 Data sheet ( Hoja de datos )
| Número de pieza | ISL8118 | |
| Descripción | Single-Phase PWM Controller | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
3.3V to 20V, Single-Phase PWM Controller
with Integrated 2A/4A MOSFET Drivers
The ISL8118 is a single-phase PWM controller featuring an
input voltage range of +3.3V to +20V and integrated MOSFET
drivers. Utilizing voltage-mode operation with input voltage
feed-forward compensation, the ISL8118 maintains a constant
loop gain, providing optimal transient response for applications
with a wide input operating voltage range.
The output voltage can be precisely regulated down to
0.591V with a system tolerance of ±0.85% over the
commercial temperature range and line and load variations.
A external reference input is provided to bypass the internal
reference for voltage tracking or DDR memory applications.
The compact 28 Ld 5x5 QFN package, integrated linear
regulator as well as the external linear regulator drive option,
integrated differential remote sense amplifier and integrated
voltage margining with adjustable upper and lower settings
decrease external component count and reduce board
space requirements.
Programmable soft-start with pre-biased load capability,
adjustable operating frequency from 250kHz to 2MHz,
sourcing and sinking overcurrent protection, overvoltage and
undervoltage protection, and power-good indication with
programmable delay combine to make the ISL8118 a
superior choice for many power supply systems.
Pinout
ISL8118
(28 LD 5x5 QFN)
TOP VIEW
28 27 26 25 24 23 22
VSENSP 1
21 BOOT
VSENSN 2
20 TGATE
REFOUT 3
REFIN 4
SS 5
GND
BOTTOM
SIDE PAD
19 LX
18 PGND
17 BGATE
OFSP 6
16 PVCC
OFSN 7
15 EXDRV
8 9 10 11 12 13 14
ISL8118
August 1, 2006
FN6325.0
Features
• Wide Input Voltage Range: +3.3V to +20V
• High-Speed 2A/4A MOSFET Gate Drivers That Operate
from 2.9V to 5.6V
• 0.591V Internal Reference
• External Reference Input
• Input Voltage Feed-forward Compensation
• Internal Linear Regulator
• External Linear Regulator Drive Available
• High System Accuracy:
- ±0.85% over the range of 0°C to +70°C
- ±1.25% over the range of -40°C to +85°C
• Programmable Operating Frequency from 250kHz to
2MHz
• Programmable Soft-Start with Pre-biased Load Capability
• Integrated Unity-Gain Differential Remote Sense Amplifier
• Enable Input with Voltage Monitoring Capability
• Integrated Voltage Margining with Independent Upper and
Lower Settings
• Overvoltage and Undervoltage Protection
• Low-Side and High-Side MOSFET Current Sensing
• Overcurrent Protection for Sourcing and Sinking Currents
• Power-Good Indicator with Programmable Delay
• Compact 28 Ld 5x5 QFN Package
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Telecom and Datacom Servers
• Point of Load Modules
• Routers and Switchers
• High Current Distributed Power Supplies
Ordering Information
PART
NUMBER*
(Note)
PART
TEMP.
MARKING RANGE (°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL8118CRZ ISL8118CRZ 0 to 70 28 Ld 5x5 QFN L28.5x5
ISL8118IRZ ISL8118IRZ -40 to 85 28 Ld 5x5 QFN L28.5x5
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL8118
Typical Application III (Dual Data Rate I or II)
VDDQ
1.8V or 2.5V
5V
REN1
CF1
VIN
VFF
EN
LIN
RCC
DBOOT
CF2
VCC
PVCC
BOOT
TSOC
RTSOC
REN2
CF4
1K
15nF
1K
DIMM
REFIN
REFOUT
PGOOD
CPGDLY
PGDLY
RFSET
FSET
ISL8118
TGATE
CTSOC
LX
BGATE
PGND
BSOC
RBSOC
COMP CBSOC
CHFIN
Q1
Q2
CBIN
CBOOT
LOUT
CHFOUT
ROFSP
MARGIN
OFSP
RMARG
ROFSN
OFSN
CSS
SS
ZFB
C1
FB
VDIFF
VSENSP
C2
R2
VSENSN
C3 R3
R1 ZIN
CSEN
RFB
EXDRV GND GND
VTT
1.25V (DDR I)
0.9V (DDR II)
CBOUT
5 FN6325.0
August 1, 2006
5 Page 
ISL8118
Functional Description
Initialization
The ISL8118 automatically initializes upon receipt of power
without requiring any special sequencing of the input
supplies. The Power-On Reset (POR) function continually
monitors the input supply voltages (PVCC,VFF, VCC) and
the voltage at the EN pin. Assuming the EN pin is pulled to
above ~0.49V, the POR function initiates soft-start operation
after all input supplies exceed their POR thresholds.
HIGH = ABOVE POR; LOW = BELOW POR
VCC POR
VFF POR
PVCC POR
EN POR
AND
SOFT-START
FIGURE 1. SOFT-START INITIALIZATION LOGIC
With all input supplies above their POR thresholds, driving
the EN pin above 0.49V initiates a soft-start cycle. In addition
to normal TTL logic, the enable pin can be used as a voltage
monitor with programmable hysteresis through the use of the
internal 10µA sink current and an external resistor divider.
This feature is especially designed for applications that have
input rails greater than a 3.3V and require specific input rail
POR and Hysteresis levels for better undervoltage
protection. Consider for a 12V application choosing
RUP = 100kΩ and RDOWN = 5.76kΩ there by setting the
rising threshold (VEN_RTH) to 10V and the falling threshold
(VEN_FTH) to 9V, for 1V of hysteresis (VEN_HYS). Care
should be taken to prevent the voltage at the EN pin from
exceeding VCC when using the programmable UVLO
functionality.
VIN
RUP
RDOWN
VREF
Sys_Enable
IEN_HYS=10µA
Soft-start
The POR function activates the internal 38µA OTA which
begins charging the external capacitor (CSS) on the SS pin to a
target voltage of VCC. The ISL8118’s soft-start logic continues
to charge the SS pin until the voltage on COMP exceeds the
bottom of the oscillator ramp, at which point, the driver outputs
are enabled, with the bottom side MOSFET first being held low
for 200ns to provide for charging of the bootstrap capacitor.
Once the driver outputs are enabled, the OTA’s target voltage is
then changed to the margined (if margining is being used)
reference voltage (VREF_MARG), and the SS pin is ramped up
or down accordingly. This method reduces start-up surge
currents due to a pre-charged output by inhibiting regulator
switching until the control loop enters its linear region. By
ramping the positive input of the error amplifier to VCC and
then to VREF_MARG, it is even possible to mitigate surge
currents from outputs that are pre-charged above the set output
voltage. As the SS pin connects directly to the non-inverting
input of the Error Amplifier, noise on this pin should be kept to a
minimum through careful routing and part placement. To
prevent noise injection into the error amplifier the SS capacitor
should be located within 150 mils of the SS and GND pins.
Soft-start is declared done when the drivers have been enabled
and the SS pin is within ±3mV of VREF_MARG.
Power Good
The power good comparator references the voltage on the
soft-start pin to prevent accidental tripping during margining.
The trip points are shown on Figure 3. Additionally, power
good will not be asserted until after the completion of the
soft-start cycle. A 0.1µF capacitor at the PGDLY pin will add
an additional ~5ms delay to the assertion of power good.
PGDLY does not delay the deassertion of power good.
VDIFF
+15%
+9%
VREF_MARG
-9%
-15%
RUP
=
V-----E----N----_---H----Y---S--
I E N _HYS
RDOWN
=
-------R-----U----P-----•----V----E----N-----_---R---E----F--------
VEN_FTH – VEN_REF
VEN_FTH = VEN_RTH – VEN_HYS
FIGURE 2. ENABLE POR CIRCUIT
GOOD
GOOD
UV OV UV
FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW
T P G DLY
=
CP
G DLY
⋅
--1---.--5---V----
30 µ A
11 FN6325.0
August 1, 2006
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ISL8118.PDF ] | |
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