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PDF ISL6610 Data sheet ( Hoja de datos )
| Número de pieza | ISL6610 | |
| Descripción | Dual Synchronous Rectified MOSFET Drivers | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
ISL6610, ISL6610A
November 22, 2006
FN6395.0
Dual Synchronous Rectified MOSFET
Drivers
The ISL6610, ISL6610A integrates two ISL6609, ISL6609A
drivers with enable function removed and is optimized to
drive two independent power channels in a synchronous-
rectified buck converter topology. These drivers, combined
with an Intersil ISL63xx or ISL65xx multiphase PWM
controller, form a complete high efficiency voltage regulator
at high switching frequency.
The IC is biased by a single low voltage supply (5V),
minimizing driver switching losses in high MOSFET gate
capacitance and high switching frequency applications.
Each driver is capable of driving a 3nF load with less than
10ns rise/fall time. Bootstrapping of the upper gate driver is
implemented via an internal low forward drop diode,
reducing implementation cost, complexity, and allowing the
use of higher performance, cost effective N-Channel
MOSFETs. Adaptive shoot-through protection is integrated
to prevent both MOSFETs from conducting simultaneously.
The ISL6610, ISL6610A features 4A typical sink current for
the lower gate driver, enhancing the lower MOSFET gate
hold-down capability during PHASE node rising edge,
preventing power loss caused by the self turn-on of the lower
MOSFET due to the high dV/dt of the switching node.
The ISL6610, ISL6610A also features an input that
recognizes a high-impedance state, working together with
Intersil multiphase PWM controllers to prevent negative
transients on the controlled output voltage when operation is
suspended. This feature eliminates the need for the schottky
diode that may be utilized in a power system to protect the
load from negative output voltage damage.
In addition, the ISL6610As bootstrap function is designed to
prevent the BOOT capacitor from overcharging, should
excessively large negative swings occur at the transitions of
the PHASE node.
Applications
• Core Voltage Supplies for Intel® and AMD®
Microprocessors
• High Frequency Low Profile High Efficiency DC/DC
Converters
• High Current Low Voltage DC/DC Converters
• Synchronous Rectification for Isolated Power Supplies
Features
• 5V Quad N-Channel MOSFET Drives for Two
Synchronous Rectified Bridges
• Pin-to-pin Compatible with ISL6614 (12V Drive)
• Adaptive Shoot-Through Protection
• 0.4Ω On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency
- Fast Output Rise and Fall
- Low Tri-State Hold-Off Time
• BOOT Capacitor Overcharge Prevention (ISL6610A)
• Low VF Internal Bootstrap Diode
• Power-On Reset
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline
- Near Chip-Scale Package Footprint; Improves PCB
Utilization, Thinner Profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Related Literature
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packages”
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Ordering Information
PART
NUMBER
(Note)
ISL6610CBZ
PART
MARKING
6610CBZ
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
0 to +70 14 Ld SOIC
PKG.
DWG. #
M14.15
ISL6610CRZ 66 10CRZ 0 to +70 16 Ld 4x4 QFN L16.4x4
ISL6610IBZ 6610IBZ -40 to +85 14 Ld SOIC M14.15
ISL6610IRZ 66 10IRZ -40 to +85 16 Ld 4x4 QFN L16.4x4
ISL6610ACBZ 6610ACBZ 0 to +70 14 Ld SOIC M14.15
ISL6610ACRZ 66 10ACRZ 0 to +70 16 Ld 4x4 QFN L16.4x4
ISL6610AIBZ 6610AIBZ -40 to +85 14 Ld SOIC M14.15
ISL6610AIRZ 66 10AIRZ -40 to +85 16 Ld 4x4 QFN L16.4x4
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
AMD® is a registered trademark of Advanced Micro Devices, Inc. All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6610, ISL6610A
Electrical Specifications These specifications apply for TA = -40°C to +85°C, unless otherwise noted (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
Tri-state to UG/LG Rising Propagation Delay
OUTPUT (Note 4)
tPDHU
tPDHL
tPTS
Outputs Unloaded
Outputs Unloaded
Outputs Unloaded
- 18
- 23
- 20
Upper Drive Source Resistance
RUG_SRC 250mA Source Current
Upper Drive Sink Resistance
RUG_SNK 250mA Sink Current
Lower Drive Source Resistance
RLG_SRC 250mA Source Current
Lower Drive Sink Resistance
RLG_SNK 250mA Sink Current
NOTE:
4. Guaranteed by Characterization. Not 100% tested in production.
- 1.0
- 1.0
- 1.0
- 0.4
MAX
-
-
-
2.5
2.5
2.5
1.0
UNITS
ns
ns
ns
Ω
Ω
Ω
Ω
Functional Pin Description
PACKAGE PIN #
PIN
SOIC DFN SYMBOL
FUNCTION
1 15 PWM1 The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during
operation, see the Tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM
output of the controller.
2 16 PWM2 The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during
operation, see the Tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM
output of the controller.
3 1 GND Bias and reference ground. All signals are referenced to this node.
4 2 LGATE1 Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.
5 3 PVCC This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor
from this pin to PGND.
6 4 PGND Power ground return of both low gate drivers.
- 5,8 NC1,2 No connection.
7 6 LGATE2 Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.
8 7 PHASE2 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This
pin provides a return path for the upper gate drive.
9 9 UGATE2 Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.
10 10 BOOT2 Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this
pin and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the
Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
11 11 BOOT1 Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this
pin and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the
Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
12 12 UGATE1 Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.
13 13 PHASE1 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This
pin provides a return path for the upper gate drive.
14 14 VCC Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR
ceramic capacitor from this pin to GND.
- 17 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5 FN6395.0
November 22, 2006
5 Page 
ISL6610, ISL6610A
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
E
-B-
H
0.25(0.010) M B M
123
-A- D
SEATING PLANE
A
L
h x 45o
-C-
e A1
B
0.25(0.010) M C A M B S
α
0.10(0.004)
C
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.0532 0.0688 1.35
1.75
-
A1 0.0040 0.0098 0.10 0.25
-
B 0.013 0.020 0.33 0.51
9
C
0.0075 0.0098 0.19
0.25
-
D
0.3367 0.3444 8.55
8.75
3
E
0.1497 0.1574 3.80
4.00
4
e 0.050 BSC 1.27 BSC -
H
0.2284 0.2440 5.80
6.20
-
h
0.0099 0.0196 0.25
0.50
5
L 0.016 0.050 0.40 1.27
6
N 14
14 7
α 0o 8o 0o 8o -
Rev. 0 12/93
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11 FN6395.0
November 22, 2006
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ISL6610.PDF ] | |
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