ISL84762 Datasheet PDF - Intersil Corporation
| Part Number | ISL84762 | |
| Description | Dual SPDT Analog Switch | |
| Manufacturers | Intersil Corporation | |
| Logo |  |
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®
Data Sheet
November 30, 2004
ISL84762
FN6105.0
Ultra Low ON-Resistance, Low Voltage,
Single Supply, Dual SPDT Analog Switch
The Intersil ISL84762 device is a low ON-resistance, low
voltage, bidirectional, dual single-pole/double-throw (SPDT)
analog switch designed to operate from a single +1.65V to
+3.6V supply. Targeted applications include battery powered
equipment that benefit from low RON (0.35Ω) and fast
switching speeds (tON = 14ns, tOFF = 6ns). The digital logic
input is 1.8V logic-compatible when using a single +3V supply.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL84762 is offered in small form factor packages, alleviating
board space limitations.
The ISL84762 is a committed dual single-pole/double-throw
(SPDT) that consist of two normally open (NO) and two
normally (NC) switches. This configuration can be used as a
dual 2-to-1 multiplexer. The ISL84762 is pin compatible with
the MAX4762.
www.DataSheet4U.com
TABLE 1. FEATURES AT A GLANCE
ISL84762
Number of Switches
2
SW SPDT or 2-1 MUX
3V RON
3V tON/tOFF
1.8V RON
1.8V tON/tOFF
Packages
0.35Ω
12ns/5ns
0.55Ω
20ns/8ns
10 Ld 3x3 Thin DFN, 10 Ld MSOP
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
Features
• Pb-Free Available (RoHS Compliant) (see Ordering Info)
• Pin Compatible Replacement for the MAX4762
• ON Resistance (RON)
- V+ = +2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.39Ω
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55Ω
• RON Matching Between Channels. . . . . . . . . . . . . . . . 0.05Ω
• RON Flatness Across Signal Range . . . . . . . . . . . . . 0.043Ω
• Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +3.6V
• Low Power Consumption (PD . . . . . . . . . . . . . . . . . <0.02µW
• Fast Switching Action (V+ = +2.7V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ns
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >9kV
• Guaranteed Break-before-Make
• 1.8V Logic Compatible (+3V supply)
• Available in 10 lead 3x3 Thin DFN and 10 lead MSOP
Applications
• Battery powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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ISL84762
Test Circuits and Waveforms
LOGIC
INPUT
V+
0V
50%
tOFF
tr < 5ns
tf < 5ns
SWITCH
INPUT
VNO
SWITCH
OUTPUT 0V
VOUT
90%
tON
90%
Logic input waveform is inverted for switches that have the opposite
logic sense.
V+
C
SWITCH
INPUT
LOGIC
INPUT
NO or NC
IN
GND
COM
VOUT
RL CL
50Ω 35pF
Repeat test for all switches. CL includes fixture and stray
capacitance.
VOUT = V(NO or NC) -R----L-----+--R--R---L--(--O-----N----)
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
FIGURE 1B. TEST CIRCUIT
V+
C
SWITCH
OUTPUT
VOUT
LOGIC
INPUT
ON
∆VOUT
OFF
V+
ON
0V
RG NO or NC
COM
VG
GND
IN
LOGIC
INPUT
Q = ∆VOUT x CL
FIGURE 2A. MEASUREMENT POINTS
Repeat test for all switches.
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
VOUT
CL
V+
C
LOGIC
INPUT
V+
0V
VNX
NO
NC
IN
COM
VOUT
RL CL
50Ω 35pF
SWITCH
OUTPUT
VOUT
0V
90%
tD
FIGURE 3A. MEASUREMENT POINTS
LOGIC
INPUT
GND
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
5 FN6105.0
November 30, 2004
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| Information | Total 11 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ ISL84762.PDF Datasheet ] | |
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