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PDF ISL45042 Data sheet ( Hoja de datos )
| Número de pieza | ISL45042 | |
| Descripción | LCD Module Calibrator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
November 14, 2006
ISL45042
FN6072.6
LCD Module Calibrator
The VCOM voltage of an LCD panel needs to be adjusted to
remove flicker. The ISL45042 can be used to digitally adjust
a panel’s VCOM voltage by controlling its output sink-
current. The output of the ISL45042 is connected to an
external voltage divider and an external VCOM buffer
amplifier. In this application, the user can control the VCOM
voltage with 7 Bit accuracy (128 steps). Once the desired
VCOM setting is obtained, the settings can be stored in the
non-volatile EEPROM memory, which would then be
automatically recalled during every power-up.
The VCOM adjustment and non-volatile memory
programming is through a single interface pin (CTL). Once
the desired programmed value is obtained the Counter
Enable pin (CE) can be used to prevent further adjustment
or programming.
The full-scale sink current of the ISL45042 is set using an
external resister connected to the SET pin. The full-scale
sink current determines the lowest voltage of the external
voltage divider.
The ISL45042 is available in an 8 Ld 3mmx3mm Thin DFN
www.DataSheet4U.copmackage with a maximum thickness of 0.8mm for ultra thin
LCD panel design.
Pinout
ISL45042
(8 LD THIN DFN)
TOP VIEW
OUT 1
AVDD 2
N/C 3
GND 4
8 SET
7 CE
6 CTL
5 VDD
Features
• 128-Step Adjustable Sink Current Output
• 2.6V to 3.6V Logic Supply Voltage Operating Range
• 4.5V to 20V Analog Supply Voltage Range
• Rewritable EEPROM for storing the optimum VCOM value
• Output Adjustment Enable/Disable Control
• Output Guaranteed Monotonic Over Temperature
• Two Pin Adjustment, Programming and Enable
• Ultra Thin 8 Ld 3mmx3mm DFN (0.8mm max)
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• LCD Panels
Ordering Information
TEMP.
PART RANGE
PART NUMBER MARKING (°C)
PACKAGE
PKG.
DWG. #
ISL45042IR
042I
-40 to +85 8 Ld 3x3 Thin DFN L8.3x3A
ISL45042IR-T 042I
-40 to +85 8 Ld 3x3 Thin DFN L8.3x3A
Tape and Reel
ISL45042IRZ
(Note)
042Z
-40 to +85 8 Ld 3x3 Thin DFN L8.3x3A
(Pb-free)
ISL45042IRZ-T 042Z
(Note)
-40 to +85 8 Ld 3x3 Thin DFN L8.3x3A
Tape and Reel
(6k pcs) (Pb-free)
ISL45042IRZ-TK 042Z
(Note)
-40 to +85 8 Ld 3x3 Thin DFN L8.3x3A
Tape and Reel
(1k pcs) (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2005-2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL45042
CTL VOLTAGE
4.9V
>200µs
CTLPT
TIME
FIGURE 2. EEPROM PROGRAMMING
When the part is programmed, the counter setting is loaded
into the non-volatile memory. This value will be loaded from
the nonvolatile memory during initial power-up or when the
CE pin is pulled low.
Once the programming is completed it is recommended that
the user float the CLT pin. The CTL pin is internally tied to a
resistor network connected to ground. If left floating, the
voltage at the CTL pin will equal VDD/2. Under these
conditions, no additional pulses will be seen by the Up/Down
counter via the CTL pin. To prevent further programming
ground the CE pin.
CTL should have a noise filter to reduce bouncing or noise
on the input that could cause unwanted counting when the
CE pin is high. The board should have an additional ESD
protection circuit, with a series 1kΩ resistor and a shunt
0.01µF capacitor connected on the CTL pin. (See Figure 3)
1kΩ
0.01µF
ISL45042
CTL
FIGURE 3. EXTERNAL ESD PROTECTION ON CTL PIN
To avoid unintentional adjustment, the ISL45042 guarantees
to reject CTL pulses shorter than 20µs.
During Initial Power-up (only), to avoid the possibility of a
false pulse (since the internal comparators come up in an
unknown state) the very first CTL pulse is ignored. See
Figure 6 for the timing information.
CE Pin
To adjust the output voltage, the CE pin must be pulled high
(VDD). The CE pin has an internal pull-down resistor to
prevent unwanted reprogramming of the EEPROM. The
impedance of this resistor is 400kΩ to 500kΩ (RINTERNAL
Figure 5).
Transitions of the CE pin are recommended to be less than
10μ seconds.
Replacing Existing Mechanical Potentiometer
Circuits
Figure 4 shows the common adjustment mechanical circuits
and equivalent replacement with the ISL45042.
Expected Output Voltage
The ISL45042 provides an output sink current which lowers
the voltage on the external voltage divider (VCOM output
voltage). EQ. 1 and EQ. 2 can be used to calculate the
output current (IOUT) and output voltage (VOUT) values.
IOUT
=
S-----e----t--t--i--n----g-
128
X
2----0--A--(--R-V----SD----E-D----T----)
(EQ. 1)
VOUT
=
⎛
⎝
R-----1---R--+---2--R-----2--⎠⎞
A V D D ⎝⎛ 1
–
S-----e----t--t--i--n----g-
128
X
2----0----(--R-R----S-1---E-----T----)⎠⎞
(EQ. 2)
NOTE: Where setting is an integer between 1 and 128.
AVDD
Ra
VCOM
-
Rb +
Rc
R1 = Ra
R2 = Rb + Rc
AVDD
ISL45042
SET
OUT
RSET
AVDD
R1
R2
-
+
VCOM
RSET = (Ra(Rb + Rc)) / 20Rb
FIGURE 4. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING THE ISL45042
5 FN6072.6
November 14, 2006
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet ISL45042.PDF ] | |
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