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PDF ISL45041 Data sheet ( Hoja de datos )
| Número de pieza | ISL45041 | |
| Descripción | TFT-LCD I2C Programmable VCOM Calibrator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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DATASHEET
TFT-LCD I2C Programmable VCOM Calibrator
ISL45041
The VCOM voltage of an LCD panel needs to be adjusted to
remove flicker. This part provides a digital interface to control
the sink current output that attaches to an external voltage
divider. The increase in output sink current lowers the voltage
on the external divider, which is applied to an external VCOM
buffer amplifier. The
external source via a
dsetasnirdeadrdVC2O-wMirseetIt2iCngseisrilaolaidnetedrffarocme.
an
At
power-up, the part automatically comes up at the last
programmed EEPROM setting.
An external resistor attaches to the SET pin and sets the
full-scale sink current that determines the lowest voltage of
the external voltage divider.
The ISL45041 is available in an 8 Ld 3mmx3mm TDFN
package with a maximum thickness of 0.8mm for ultra thin
LCD panel design.
An evaluation kit complete with software to control the DCP
from a computer is available. Reference Application Note
AN1275 and “Ordering Information” on page 2.
Features
• 128-step adjustable sink current output
• 2.25V to 3.6V logic supply voltage operating range (2.6V
minimum programming voltage)
• 4.5V to 18V analog supply voltage operating range (10.8V
minimum programming voltage)
• I2C interface with addresses 100111x and 100110x
• On-chip 7-Bit EEPROM
• Output adjustment SET pin
• Output guaranteed monotonic over-temperature
• Thin 8 Ld 3mmx3mm DFN (0.8mm max)
• Pb-free (RoHS compliant)
Applications
• LCD panels
Related Literature
• AN1208 “LCD screens don't flicker - or do they?”
• AN1244, “ISL45041 and ISL29001 Flicker Control User’s
Manual”
• AN1275, “ISL45041EVAL1Z User’s Manual”
VDD
5
AVDD
2
SDA
SCL
6
7
3
WP
I2C
INTERFACE
DAC
REGISTERS
ANALOG DCP
AND
CURRENT SINK
Q1
CURRENT SINK
7-BIT EEPROM
A1
ISL45041
4
GND
FIGURE 1. BLOCK DIAGRAM
1
OUT
8
SET
October 30, 2014
FN6189.5
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC. 2005- 2007, 2010, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL45041
Application Information
This device provides the ability to reduce the flicker of an LCD
panel by adjustment of the VCOM voltage during production test
and alignment. A 128-step resolution is provided under digital
control, which adjusts the sink current of the output. The output is
connected to an external voltage divider, so that the device will
have the capability to reduce the voltage on the output by
increasing the output sink current.
AVDD
AVDD
ISL45041
SET
OUT
RSET
IOUT
R1
R2
-
+
FIGURE 2. OUTPUT CONNECTION CIRCUIT EXAMPLE
The adjustment of the output is provided by the 2-wire I2C serial
interface.
Expected Output Voltage
The ISL45041 provides an output sink current, which lowers the
voltage on the external voltage divider (VCOM output voltage).
Equations 1 and 2 can be used to calculate the output current
(IOUT) and output voltage (VOUT) values. The setting is the register
value +1 with a value between 1 and 128.
IOUT
=
S-----e----t--t--i--n----g-
128
x
------A----V-----D----D-------
20 RS E T
(EQ. 1)
VOUT
=
-R----1--R---+--2--R-----2-
AVD
D
1
–
S-----e----t--t--i--n----g-
128
x
-2---0------R-R----S1----E---T----
(EQ. 2)
Table 1 gives the calculated value of VOUT using the resistor values
of: RSET = 24.9kΩ, R1 = 200kΩ, R2 = 243kΩ and AVDD = 10V.
TABLE 1.
SETTING VALUE
VOUT
(V)
1 5.468
10 5.313
20 5.141
30 4.969
40 4.797
50 4.625
60 4.453
70 4.281
80 4.109
90 3.936
100 3.764
110 3.592
128 3.282
RSET Resistor
The external RSET resistor sets the full-scale sink current, ISET
maximum, that determines the lowest voltage of the external
voltage divider R1 and R2 (Figure 2). The voltage difference between
the OUT pin and SET pin (Figure 3), which are also the drain and
source of the output transistor, must be greater than 1.75V. This will
keep the output transistor in its saturation region to maintain linear
operation over the full range of register values. Expected current
settings and 7-bit accuracy occurs when the output MOS transistor is
operating in the saturation region. Figure 3 shows the internal
connection for the output MOS transistor. The value of the AVDD
supply sets the voltage at the source of the output transistor. This
voltage is equal to (Setting/128) x (AVDD/20). The ISET current is
therefore equal to (Setting/128) x (AVDD/20 x RSET). The drain
voltage is calculated using Equation 2. The values of R1 and R2
(Equation 2) should be determined using IOUT maximum (setting
equal to 128) so the minimum value of VOUT is greater than 1.75V +
AVDD/20.
S-----E----T-----T----I--N-----G--- x A-----V-----D----D---
128 20
OUT PIN
AVDD = 15V
R1
AVDD
VSAT
0.5V
R2
RSET
SET PIN
FIGURE 3. OUTPUT CONNECTION CIRCUIT EXAMPLE
Ramp-Up of the VDD Power Supply
The ramp-up from 10% VDD to 90% VDD level must be achieved
in 10ms or less to ensure that the EEPROM and power-on-reset
circuits are synchronized and the correct value is read from the
EEPROM Memory.
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 3. When applying power, VDD should be applied before or
at the same time as AVDD. The minimum time for tVS is 0µs.
When removing power, the sequence of VDD and AVDD is not
important.
VDD
AVDD
tVS
FIGURE 3. POWER SUPPLY SEQUENCE
Do not remove VDD or AVDD within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
Submit Document Feedback
5
FN6189.5
October 30, 2014
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet ISL45041.PDF ] | |
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