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PDF ISL22319 Data sheet ( Hoja de datos )
| Número de pieza | ISL22319 | |
| Descripción | Low Noise Low Power Bus 128 Taps | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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ISL22319
® Single Digitally Controlled Potentiometer (XDCP™)
Data Sheet
July 3, 2006
FN6310.0
Low Noise, Low Power, I2C® Bus,
128 Taps, Wiper Only
The ISL22319 integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the content of the
DCP’s IVR to the WR.
The DCP can be used as a voltage divider in a wide variety
of applications including control, parameter adjustments, AC
measurement and signal processing.
Pinout
www.DataSheet4U.com
ISL22319
(8 LD MSOP)
TOP VIEW
SCL
SDA
A1
A0
1
2
3
4
8 VCC
7 RW
6 SHDN
5 GND
Features
• 128 resistor taps
• I2C serial interface
- Two address pins, up to four devices/bus
• Non-volatile storage of wiper position
• Wiper resistance: 70Ω typical @ 3.3V
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ or 10kΩ total resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T ≤ 55 °C
• 8 Ld MSOP
• Pb-free plus anneal product (RoHS compliant)
Ordering Information
PART NUMBER
PART MARKING
RESISTANCE OPTION
(kΩ)
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
ISL22319UFU8Z
(Notes 1, 2)
319UZ
50
-40 to +125
8 Ld MSOP
M8.118
(Pb-Free)
ISL22319WFU8Z
(Notes 1, 2)
319WZ
10
-40 to +125
8 Ld MSOP
M8.118
(Pb-Free)
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for 1,000 Tape and Reel option
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL22319
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (NOTE 5)
Hysteresis SDA and SCL Input Buffer Hysteresis
VOL SDA Output Buffer LOW Voltage,
Sinking 4mA
0.05*
VCC
0
Cpin
A1, A0, SHDN, SDA, and SCL Pin
Capacitance
fSCL
tsp
SCL Frequency
Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is
and SCL Inputs
suppressed
tAA
tBUF
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until
Valid
SDA exits the 30% to 70% of VCC window
Time the Bus Must be Free before the SDA crossing 70% of VCC during a STOP
Start of a New Transmission
condition, to SDA crossing 70% of VCC
during the following START condition
1300
tLOW
tHIGH
tSU:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
Measured at the 30% of VCC crossing
Measured at the 70% of VCC crossing
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
1300
600
600
600
100
0
tSU:STO
tHD:STO
tDH
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge;
or Volatile Only Write
both crossing 70% of VCC
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
600
1300
0
tR SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
tF SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
Rpu SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF
Off-chip
For Cb = 400pF, max is about 2~2.5kΩ
For Cb = 40pF, max is about 15~20kΩ
1
tSU:A
tHD:A
A1 and A0 Setup Time
A1 and A0 Hold Time
Before START condition
After STOP condition
600
600
MAX
0.4
10
400
50
900
250
250
400
UNIT
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
kΩ
ns
ns
NOTES:
5. Typical values are for TA = 25°C and 3.3V supply voltage.
6. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
7. ZS error = V(RW)0/LSB.
5 FN6310.0
July 3, 2006
5 Page 
ISL22319
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
SIGNALS FROM
THE SLAVE
WRITE
S
T
A IDENTIFICATION
R BYTE
T
ADDRESS
BYTE
0 1 0 1 0 A1 A0 0 0 0 0 0
A
C
K
A
C
K
FIGURE 14. BYTE WRITE SEQUENCE
DATA
BYTE
S
T
O
P
A
C
K
SIGNALS
FROM THE
MASTER
S
T
A IDENTIFICATION
R BYTE WITH
T R/W=0
ADDRESS
BYTE
S
T
A IDENTIFICATION
R BYTE WITH
T R/W=1
A
C
K
SIGNAL AT SDA 0 1 0 1 0A1 A0 0
0000
SIGNALS FROM
THE SLAVE
A
C
K
0 1 0 1 0 A1 A0 1
AA
C C FIRST READ
K K DATA BYTE
FIGURE 15. READ SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22319 responds with an ACK. At this time, the device
enters its standby state (See Figure 14).
The non-volatile write cycle starts after STOP condition is
determined and it requires up to 20ms delay for the next
non-volatile write.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (See Figure 15). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL22319 responds with an ACK. Then
the ISL22319 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a ACK and STOP condition) following the
last bit of the last Data Byte (See Figure 15).
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
A
C
K
S
AT
CO
KP
LAST READ
DATA BYTE
11 FN6310.0
July 3, 2006
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ISL22319.PDF ] | |
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