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What is ISL22316?

This electronic component, produced by the manufacturer "Intersil Corporation", performs the same function as "Single Digitally Controlled Potentiometer".


ISL22316 Datasheet PDF - Intersil Corporation

Part Number ISL22316
Description Single Digitally Controlled Potentiometer
Manufacturers Intersil Corporation　
Logo Intersil Corporation Logo　


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Data Sheet
ISL22316
Single Digitally Controlled Potentiometer (XDCP™)
August 14, 2015
FN6186.3
Low Noise, Low Power I2C™ Bus,
128 Taps
The ISL22316 integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up, the device recalls the contents of the
DCP’s IVR to the WR.
The DCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Pinouts
SCL
SDA
A1
A0
SHDN
ISL22316
(10 LD MSOP)
TOP VIEW
1 10
29
38
47
56
VCC
RH
RW
RL
GND
Features
• 128 resistor taps
• I2C serial interface
- Two address pins, up to four devices/bus
• Non-volatile storage of wiper position
• Wiper resistance: 70typical @ VCC = 3.3V
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kor 10ktotal resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T +55°C
• 10 Ld MSOP or 10 Ld TDFN package
• Pb-free (RoHS compliant)
ISL22316
(10 LD TDFN)
TOP VIEW
SCL 1 O
SDA 2
A1 3
A0 4
SHDN 5
10 VCC
9 RH
8 RW
7 RL
6 GND
Ordering Information
PART NUMBER
(Note)
PART
MARKING
RESISTANCE OPTION
(k)
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG. DWG. #
ISL22316UFU10Z*
(No longer available,
recommended
replacement:
(ISL22316WFRT10Z-TK)
316UZ
50
-40 to +125
10 Ld MSOP
M10.118
ISL22316WFU10Z*
316WZ
10
-40 to +125
10 Ld MSOP
M10.118
ISL22316UFRT10Z*
(No longer available,
recommended
replacement:
(ISL22316WFRT10Z-TK)
316U
50
-40 to +125
10 Ld 3x3 TDFN
L10.3x3B
ISL22316WFRT10Z*
316W
10
-40 to +125
10 Ld 3x3 TDFN
L10.3x3B
*Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2006, 2008, 2009, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

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ISL22316 equivalent
ISL22316
Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN TYP MAX
(Note 19) (Note 5) (Note 19) UNIT
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
Cycles
EEPROM Retention
Temperature T +55°C
50
Years
tWC Non-volatile Write Cycle Time
(Note 17)
12 20 ms
SERIAL INTERFACE SPECIFICATIONS
VIL A1, A0, SHDN, SDA, and SCL Input Buffer
LOW Voltage
-0.3
0.3*VCC
V
VIH A1, A0, SHDN, SDA, and SCL Input Buffer
HIGH Voltage
0.7*VCC
VCC + 0.3 V
Hysteresis SDA and SCL Input Buffer Hysteresis
VOL SDA Output Buffer LOW Voltage, Sinking
4mA
0.05*VCC
0
V
0.4 V
Cpin A1, A0, SHDN, SDA, and SCL Pin
(Note 18) Capacitance
10 pF
fSCL
tsp
SCL Frequency
Pulse Width Suppression Time at SDA and Any pulse narrower than the max spec is
SCL Inputs
suppressed
400 kHz
50 ns
tAA
tBUF
SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window
Time the Bus Must be Free Before the Start SDA crossing 70% of VCC during a STOP
of a New Transmission
condition, to SDA crossing 70% of VCC
during the following START condition
1300
900 ns
ns
tLOW
tHIGH
tSU:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
Measured at the 30% of VCC crossing
Measured at the 70% of VCC crossing
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
1300
600
600
600
100
0
ns
ns
ns
ns
ns
ns
tSU:STO STOP Condition Setup Time
tHD:STO
tDH
STOP Condition Hold Time for Read, or
Volatile Only Write
Output Data Hold Time
tR SDA and SCL Rise Time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
From SDA rising edge to SCL falling edge;
both crossing 70% of VCC
From SCL falling edge crossing 30% of
VCC, until SDA enters the 30% to 70% of
VCC window
From 30% to 70% of VCC
600
1300
0
20 +
0.1*Cb
ns
ns
ns
250 ns
tF SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1*Cb
250 ns
Cb Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10 400 pF
5 FN6186.3
August 14, 2015


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