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PDF ISL21400 Data sheet ( Hoja de datos )
| Número de pieza | ISL21400 | |
| Descripción | Programmable Temperature Slope Voltage Reference | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
December 14, 2006
ISL21400
FN8091.0
Programmable Temperature Slope
Voltage Reference
The ISL21400 features a precision voltage reference
combined with a temperature sensor whose output voltage
varies linearly with temperature. The precision 1.20V
reference has a very low temperature coefficient (tempco),
and its output voltage is scaled by an internal DAC (VREF) to
produce a temperature stable output voltage that is
programmable from 0V to 1.20V. The output voltage from the
temperature sensor (VTS) is summed with VREF to produce
a temperature dependent output voltage.
The slope of the VTS portion of the output voltage can be
programmed to be positive or negative in the range
-2.1mV/°C to +2.1mV/°C. A programmable gain amplifier
(PGA) sums the VTS and the VREF voltages and provides
gains of 1x, 2x, and 4x to scale the output up to 4.8V and the
slope to ±8.4mV/°C.
The VREF and VTS terms are programmable with 8 bits of
resolution via an I2C bus and the values are stored in non-
volatile registers. The PGA gain is also set via the I2C bus
and the value is stored in a non-volatile register. Non-volatile
memory storage assures the programmed settings are
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retained on power-down, eliminating the need for software
initialization at device power-up.
Temperature Characteristics Curve
3.0
AV = 2
2.5
2.0
TS = 0
1.5
1.0
TS = 0
0.5
TS = 127
AV = 1
TS = 255
TS = 255 TS = 127
0.0
-40
-15 10
35
TEMPERATURE (°C)
60
85
Features
• Programmable reference voltage
• Programmable temperature slope
• Programmable Gain Amplifier
• Non-volatile storage of programming registers
• I2C serial interface
• 2% total accuracy over temperature and VCC range
• 200µA typical active supply current
• Operating temperature range = -40°C to +85°C
• 8 Ld MSOP package
Applications
• RF power amplifier bias compensation
• LCD bias compensation
• Laser diode bias compensation
• Sensor bias and linearization
• Data acquisition systems
• Variable DAC reference
• Amplifier biasing
Pinout
ISL21400
(8 LD MSOP)
TOP VIEW
A2 1
A1 2
A0 3
VSS 4
8 VCC
7 VOUT
6 SDA
5 SCL
Ordering Information
PART NUMBER (Note)
PART MARKING
VDD RANGE
(V)
TEMP RANGE
(°C)
PACKAGE
PKG. DWG. #
ISL21400IU8Z
DEW
2.7 to 5.5
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
ISL21400IU8Z-TK
DEW
2.7 to 5.5
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL21400
Serial Interface Specification (for SCL, SDA, A0, A1, A2 unless specified otherwise) (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (Note 2)
tsp Pulse Width Suppression Time at Any pulse narrower than the
SDA and SCL Inputs
max spec is suppressed
(Note 3)
tAA SCL Falling Edge to SDA Output SCL falling edge crossing
Data Valid
30% of VCC, until SDA exits
the 30% to 70% of VCC
window (Note 3)
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VCC
during a STOP condition, to
SDA crossing 70% of VCC
during the following START
condition (Note 3)
1300
tLOW
Clock LOW Time
Measured at the 30% of VCC
crossing (Note 3)
1300
tHIGH
Clock HIGH Time
Measured at the 70% of VCC
crossing (Note 3)
600
tSU:STA START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
tSU:STO STOP Condition Setup Time
tHD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
tDH Output Data Hold Time
tR SDA and SCL Rise Time
SCL rising edge to SDA
falling edge; both crossing
70% of VCC (Note 3)
From SDA falling edge
crossing 30% of VCC to SCL
falling edge crossing 70% of
VCC (Note 3)
From SDA exiting the 30% to
70% of VCC window, to SCL
rising edge crossing 30% of
VCC (Note 3)
From SCL rising edge
crossing 70% of VCC to SDA
entering the 30% to 70% of
VCC window (Note 3)
From SCL rising edge
crossing 70% of VCC, to SDA
rising edge crossing 30% of
VCC (Note 3)
From SDA rising edge to SCL
falling edge; both crossing
70% of VCC (Note 3)
From SCL falling edge
crossing 30% of VCC, until
SDA enters the 30% to 70%
of VCC window (Note 3)
From 30% to 70% of VCC
(Note 3)
600
600
100
0
600
1300
0
20 +
0.1 x Cb
tF SDA and SCL Fall Time
From 70% to 30% of VCC
(Note 3)
20 +
0.1 x Cb
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip
(Note 4)
10
MAX
50
900
250
250
400
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
5 FN8091.0
December 14, 2006
5 Page 
ISL21400
Register Descriptions
Addr
0
1
2
3
4
D7
(MSB)
VREF7
TS7
D7
D7
D7
D6
VREF6
TS6
D6
D6
D6
TABLE 1. ISL21400 REGISTER BIT MAP
D5
VREF5
TS5
D5
D5
D5
D4
VREF4
TS4
D4
D4
D4
D3
VREF3
TS3
D3
D3
D3
D2
VREF2
TS2
D2
D2
D2
D1
VREF1
TS1
GAIN1
D1
D1
D0
(LSB)
VREF0
TS0
GAIN0
D0
D0
REG
0
1
2
3
4
TABLE 2. REGISTER DESCRIPTIONS
NONVOLATILE
DESCRIPTION
Y Reference setting
Y Temperature Sensor setting
Y Gain and storage
Y Storage
Y Storage
Register 0: Bandgap Reference Gain (Nonvolatile)
Register 0 sets the output voltage of the bandgap reference
(VREF). Referring to Equation 1, the number “n” is the setting
from Register 0 as follows:
VREF
•
----n-----
255
,
for
n=0
to
255
This term of Equation 1 can vary from 0 to 1.20V.
Register 1: Temperature Slope Gain (Nonvolatile)
Register 1 sets the Temperature Slope (TS) of the
temperature sensor. Referring to Equation 1, the number “m”
is the setting from Register 1 as follows:
VTS
(---2-----•----m-----)---–---2---5----5--
255
VTS is the temperature dependent term and varies from
+136mV at -40°C to -126mV at +85°C. The other term varies
from -1 to +1 and scales the temperature term before adding
to the VREF portion.
Register 2: Device Gain and Storage (nonvolatile)
TABLE 3. REGISTER 2 OUTPUT GAIN (NONVOLATILE):
OUTPUT GAIN
GAIN1
0
GAIN0
0
OUTPUT GAIN, AV
x1
01
x2
10
x2
11
x4
Register 2 contains 2 bits (2 LSB’s) which control the output
gain of the device. Table 3 shows the state of these two bits
and the resulting output gain. Note that two states produce
the same gain (Gain 1:0 set to 01b and 10b) of x2.
The other 6 bits in the register can be used for general
purpose memory (nonvolatile) or left alone.
Registers 3 and 4: general purpose data
(nonvolatile)
These two registers are one byte each and can be used for
general purpose nonvolatile memory.
I2C Serial Interface
The ISL21400 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is the master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL21400
operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 10). On power-up of the ISL21400 the SDA pin is in
the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL21400 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 10). A START condition is ignored during the power-
up sequence and during non-volatile write cycles for the
device.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 10) A STOP condition at the end of
a read operation, or at the end of a write operation places
the device in its standby mode. A STOP condition at the end
of a write operation to a non-volatile byte initiates an internal
11 FN8091.0
December 14, 2006
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ISL21400.PDF ] | |
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