|
|
Número de pieza | ISPPAC-CLK56xx | |
Descripción | In-System Programmable | |
Fabricantes | Lattice Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de ISPPAC-CLK56xx (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! ispClock™5600 Family
In-System Programmable, Zero-Delay Clock Generator
with Universal Fan-Out Buffer
November 2004
Preliminary Data Sheet
Features
■ 10MHz to 320MHz Input/Output Operation
■ Low Output to Output Skew (<50ps)
■ Low Jitter Peak-to-Peak (<60ps)
■ Up to 20 Programmable Fan-out Buffers
• Programmable output standards and individual
enable controls
- LVTTL, LVCMOS, HSTL, SSTL, LVDS,
LVPECL
• Programmable output impedance
- 40 to 70Ω in 5Ω increments
• Programmable slew rate
• Up to 10 banks with individual VCCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
■
www.DataSheet4U.com
Fully Integrated High-Performance PLL
• Programmable lock detect
• Multiply and divide ratio controlled by
- Input divider (5 bits)
- Feedback divider (5 bits)
- Five output dividers (5 bits)
• Programmable On-chip Loop Filter
■ Precision Programmable Phase Adjustment
(Skew) Per Output
• 16 settings; minimum step size 195ps
- Locked to VCO frequency
Product Family Block Diagram
• Up to +/- 12ns skew range
• Coarse and fine adjustment modes
■ Up to Five Clock Frequency Domains
■ Flexible Clock Reference and External
Feedback Inputs
• Programmable input standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL
• Clock A/B selection multiplexer
• Feedback A/B selection multiplexer
• Programmable termination
■ Four User-programmable Profiles Stored in
E2CMOS® Memory
• Supports both test and multiple operating
configurations
■ Full JTAG Boundary Scan Test In-System
Programming Support
■ Exceptional Power Supply Noise Immunity
■ Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
■ 100-pin and 48-pin TQFP Packages
■ Applications
• Circuit board common clock generation and
distribution
• PLL-based frequency generation
• High fan-out clock buffer
• Zero-delay clock buffer
LOCK DETECT
OUTPUT
BYPASS
DIVIDERS
V0
SKEW
OUTPUT
CONTROL DRIVERS
MUX
V1
M
*
PHASE/
V2
FREQUENCY
FILTER
VCO
DETECTOR
V3
N
PLL CORE
V4
OUTPUT
ROUTING
MATRIX
Internal/External
Feedback
Select
JTAG
INTERFACE
&
Multiple Profile
Management Logic
*
E2CMOS
MEMORY
0123
* Input Available only on ispClock5620
INTERNAL FEEDBACK PATH
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
clk5600_01
1 page Lattice Semiconductor
ispClock5600 Family Data Sheet
Performance Characteristics – Power Supply
Symbol
Parameter
Conditions
Typ.
ICCD
Core Supply Current
fVCO = 640MHz
150
ICCA
Analog Supply Current
fVCO = 640MHz
5.5
ICCO
Output Driver Supply Current
(per Bank)
VCCO = 1.8V1, LVCMOS
VCCO = 2.5V1, LVCMOS
VCCO = 3.3V1, LVCMOS
VCCO = 3.3V2, LVDS
13
18
24
7.5
VCCJ = 1.8V
ICCJ JTAG I/O Supply Current (static) VCCJ = 2.5V
VCCJ = 3.3V
200
300
300
1. Supply current consumed by each bank, both outputs active, 18pF load, 320MHz output frequency.
2. Supply current consumed by each bank, 100Ω, 5pf differential load, 320MHz output frequency.
Max.
160
7
15
24
35
8
300
400
400
Units
mA
mA
mA
µA
DC Electrical Characteristics – Single-ended Logic
Logic Standard
VIL (V)
Min.
Max.
VIH (V)
Min.
Max.
LVTTL/LVCMOS 3.3V -0.3
0.8
2
3.6
LVCMOS 1.8V
LVCMOS 2.5V
-0.3 0.35VCCO 0.65VCCO
-0.3 0.7
1.7
3.6
3.6
SSTL2 Class 1
-0.3 VREF - 0.18 VREF + 0.18
SSTL3 Class 1
-0.3 VREF - 0.2 VREF + 0.2
HSTL Class 1
-0.3 VREF - 0.1 VREF + 0.1
1. Specified for 50Ω internal series output termination.
2. Specified for 40Ω internal series output termination.
3. Specified for ≈20Ω internal series output termination.
3.6
3.6
3.6
VOL Max. (V) VOH Min. (V)
0.4 VCCO - 0.4
0.4 VCCO - 0.4
0.4 VCCO - 0.4
0.542
VCCO - 0.812
0.92 VCCO - 1.32
0.43 VCCO - 0.43
IOL (mA)
41
41
41
7.6
8
8
IOH (mA)
-41
-41
-41
-7.6
-8
-8
DC Electrical Characteristics – LVDS
Symbol
Parameter
Conditions
VICM
VTHD
VIN
VOH
VOL
VOD
∆VOD
VOS
∆VOS
ISA
ISAB
Common Mode Input Voltage
Differential Input Threshold
Input Voltage
Output High Voltage
Output Low Voltage
Output Voltage Differential
Change in VOD between H and L
Output Voltage Offset
RT = 100Ω
RT = 100Ω
RT = 100Ω
Common Mode Output Voltage
Change in VOS Between H and L
Output Short Circuit Current
Output Short Circuit Current
VOD = 0V, Outputs Shorted to GND
VOD = 0V, Outputs Shorted to Each Other
Min.
0.05
±100
0
—
0.9
250
—
1.125
—
—
—
Typ.
—
—
—
1.375
1.03
400
—
1.20
—
—
—
Max.
2.35
—
2.4
1.60
—
480
50
1.375
50
24
12
Units
V
mV
V
V
V
mV
mV
V
mV
mA
mA
5
5 Page Lattice Semiconductor
ispClock5600 Family Data Sheet
Timing Specifications
Skew Matching
Symbol
Parameter
tSKEW
Output-output Skew
Conditions
Between any two identically configured and loaded
outputs regardless of bank.
Min.
—
Typ.
—
Max.
50
Units
ps
Programmable Skew Control
Symbol
Parameter
Conditions
Min.
Typ.
tSKRANGE
SKSTEPS
tSKSTEP
tSKERR
Skew Control Range1
Skew Steps per range
Skew Step Size2
Skew Time Error3
Fine Skew Mode, fVCO = 320 MHz
Fine Skew Mode, fVCO = 640 MHz
Coarse Skew Mode, fVCO = 320 MHz
Coarse Skew Mode, fVCO = 640 MHz
Fine Skew Mode, fVCO = 320 MHz
Fine Skew Mode, fVCO = 640 MHz
Coarse Skew Mode, fVCO = 320 MHz
Coarse Skew Mode, fVCO = 640 MHz
Fine skew mode
Coarse skew mode
—
—
—
—
—
—
—
—
—
—
—
5.86
2.93
11.72
5.86
16
390
195
780
390
30
50
1. Skew control range is a function of VCO frequency (fVCO). In fine skew mode TSKRANGE = 15/(8 x fVCO).
In coarse skew mode TSKRANGE = 15/(4 x fVCO).
2. Skew step size is a function of VCO frequency (fVCO). In fine skew mode TSKSTEP = 1/(8 x fVCO).
In coarse skew mode TSKSTEP = 1/(4 x fVCO).
3. Only applicable to outputs with non-zero skew settings.
Max.
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ps
ps
Control Functions
Symbol
Parameter
tDIS/OE
Delay Time, OEX or OEY to Output Disabled/
Enabled
tDIS/GOE
tSUSGATE
Delay Time, GOE to Output Disabled/Enabled
Setup Time, SGATE to Output Clock Start/
Stop
tPLL_RSTW
PLL Reset Pulse Width2
tRSTW
Logic Reset Pulse Width3
tHPS_RST
Hold time for RESET past change in PS[0..1]
1. Output clock cycles for the particular output being controlled.
2. Will completely reset PLL.
3. Will only reset digital logic.
Conditions
Min.
—
—
3
1
20
20
Typ.
10
10
—
—
—
—
Max. Units
20 ns
20 ns
— cycles1
— ms
— ns
— ns
Figure 6. RESET and Profile Select Timing
PS[0..1]
RESET
tHPS_RST
tPLL_RSTW
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet ISPPAC-CLK56xx.PDF ] |
Número de pieza | Descripción | Fabricantes |
ISPPAC-CLK56xx | In-System Programmable | Lattice Semiconductor |
ISPPAC-CLK56xxA | In-System Programmable | Lattice Semiconductor |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |